Before (at 1.024 Gbps) it had slipped in one direction at 210 MHz and the other direction at 290 MHz. This indicated that there was a clock rate problem.
Once it was running at 200MHz the slipping was random. Random slipping indicated to me there was also a signal integrity problem and the clock rate problem was fixed.
I had soldered a termination resistor on that proto-board (0201... yikes!) because #Xilinx doesn't allow internal resistors on this bank.
On a hunch I added attenuators...