PSA: This just landed on my work feed:

Zynq UltraScale+ Design Advisory

https://adaptivesupport.amd.com/s/article/72992?language=en_US

#FPGA #Xilinx #vhdl #verilog #pcie

Advent of Code 2025 Day 2 in FPGA 🤓 github.com/JulianKemmer... #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

github.com/JulianKemmerer...

Advent of Code 2025 Day 2 in FPGA 🤓

https://github.com/JulianKemmerer/PipelineC/blob/master/examples/aof25/day2.c

#fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

@madduci @vitaut

'don't care', 'unknown', strong 0, strong 1, high impedance, weak 0, weak 1, weak conflicting, strong conflicting.

Or: the voting options when C++ committee members make up their mind on a proposal. 😹

#cpp #vhdl

Here we (finally) go:

This is Klee (used to be called Layla, but Klee fits better due to the color and board name). She is a BeagleV-Fire and without any competition the coolest SBC I own:

She has a RISC-V processor (already pretty cool) that is combined with an FPGA (incredibly cool). Therefore, I can write my own logic and basically add it to the processor. The main processor can access any custom logic using memory mapped IO (either using ABP or AXI4) and it can even access the main memory (only with AXI).
There is also an M.2 expansion slot (accessed and controlled using the FPGA fabric btw!), so I could add any PCIE device, even a GPU! Lastly, she also has a very weird connector called SYZYGY, which can be used for very high speed IO stuff, but sadly all the peripherals for it are insanely expensive.

Her only downsides are the lack of RAM (only 2GB), the relatively slow processor, the relatively small FPGA (compared to some of the Xilinx ones), and the tools used for the synthesis flow requiring a (free) license and being very annoying to use.

But all in all I absolutely adore this SBC and I love writing my own custom hardware components for it!

S'il vous plaît, faites nous des interfaces de configurations sous forme de fichiers texte.

Que je puisse tout configurer dans un fichier que je versionne proprement avec git et que je n'ai plus qu'à lancer un script pour générer les bitstream et autre fichiers de config.

J'en peu plus de ces clic-clic ultra-buggés en vieux java qui s'affichent mal et mettent des plombes à cocher/décocher.

Sans parler des messages d'erreurs obscures qui surgissent qu'au bout de 30 min de calcul !

#quartus #intel #vivado #amd #xilinx #fgpa #flf #liberté #vhdl #verilog #java #bitstream

Nous sommes en 2025 et Intel/Altera ne propose toujours pas de logiciel libres pour la simulation des projets Quartus (25.3) :(

Dommage.

#quartus #altera #questasim #vhdl #verilog #simulation #FPGA #flf #vcs #xcelium #rivierapro #intel

CHIP8 – writing emulator, assembler, example game and VHDL hardware impl

http://blog.dominikrudnik.pl/chip8-emulator-assembler-game-vhdl

#HackerNews #CHIP8 #Emulator #Assembler #VHDL #Game #Development

🌘 打造 CHIP-8 模擬器、組譯器與 VHDL 硬體實現
➤ 從 VHDL 硬體到 C 語言模擬器與組譯器，一步步拆解 CHIP-8 的奧祕
✤ http://blog.dominikrudnik.pl/chip8-emulator-assembler-game-vhdl
作者分享了其學習電腦系統原理的個人專案，成功用 VHDL 實現了 CHIP-8 虛擬機的硬體架構，同時也開發了對應的 C 語言模擬器和 C++ 組譯器。這個專案旨在深入理解低階運作機制，而非追求生產就緒的效能，作者透過逐一實現 CHIP-8 的指令集，並處理繪圖等複雜功能，來鞏固其對電腦架構的掌握。
+ 這個專案的教育價值很高！能親手用 VHDL 實作硬體，再用 C 語言模擬，最後還有組譯器，對理解電腦底層架構非常有幫助。
+ 雖然作者提到不是生產級別的程式碼，但其對 opcode 的拆解和繪圖指令的實現細節寫得非常清楚，對於想學習 CHIP-8 的開發者來說是個絕佳的參考。
#模擬器 #組譯器 #VHDL #CHIP-8 #硬體實現

After *checks notes* 8 months, I finally got around to doing another Surfer release 🎉

The change log is long with lots of big and small changes, my favorites being the new wasm based translators, and improvements to the waveform control protocol.

I also took the opportunity to set up automatic builds of the VSCode extension from `main` so it will be in sync with the rest of our binaries :)

Full change log at https://gitlab.com/surfer-project/surfer/-/blob/main/CHANGELOG.md?ref_type=heads#040---2025-11-06

#fpga #asic #verilog #vhdl

Attended "An Open Source RISC-V CPU in FPGA" by Kristoffer Robin Stokke at UiO. Pure OS joy!

- 32-bit `RISC-V` CPU in open `VHDL` on a cheap FPGA
- Minimalist: UART, SDRAM, pixel screen
- All source code open

Saw the FPGA board IRL—tiny silicon, big dreams. Bare-metal computing distilled. Trying to convince Kristoffer to present this at FOSDEM!

#riscv #fpga #opensource #hardware #hacker #vhdl #baremetal

Cocotb version 2.0

https://linuxfr.org/news/sortie-de-cocotb-version-2-0-0

#Cocotb #fpga #python #vhdl #verilog #systemverilog

@guix Other than as package manager on top of #archlinux, I’m using #guix for electronics design, mostly #vhdl and #fpga related stuff.

I run simulations with help of #hdlmake using #ghdl compiler, #osvvm for verification, #cocotb for testbenches, #yosys for synthesis, #nextpnr for placement and routing and #openFPGALoader for flashing. Finally, I use my own Guix channel to package gateware and run #ci tests on #sourcehut Guix image. A demo toy example of this runs here

https://builds.sr.ht/~csantosb/job/1585413

Keeping track of progress of the Z80 Noveau FPGA-based project. Now with sprites!

Details of the sprite logic in the Z80 Nouveau VDP finite state machine Verilog modules.
This provides an implementation of a TI9118-compatible graphic display.

@ John's Basement

https://www.youtube.com/watch?v=NmcVoH9CotA

#z80 #z80nouveau #sprites #fpga #verilog #vhdl

@carlosefr Really? I am usually happy to delegate code formatting to the computer.

Of course I spend a lot of time cleaning up inconsistently formatted #vhdl and #verilog. I also write a lot of #python that I just want to follow pep8 automatically.

In C I can't imagine why/how intent would be incoded in formatting unless the intent is obfuscation.

I could imagine a problem with #assembly code if you are using indents to help show conditionals, etc.

What language/example is on your mind?

Cocotb v2.0.0 \o/

https://github.com/cocotb/cocotb/releases/tag/v2.0.0

#cocotb #flf #release #python #verilog #vhdl #icarus #ghdl #nvc #verilator

Dear @PaulaMaddox, I hope you are well! I think I'm going to punt on my lvds deserializer approach. I fear I am having what look like signal integrity issues, but could also be design/fpga timing issues. Achieving lvds deserialization is not necessary, and I don't want to spend any more time fighting it.

I see Alchitry has a new Pt board with transceivers. It also has a 400Mbit USB part on an Ft+ board.

Hmm... will I face vendor lock-in? Do you have any advice?

#Xilinx #FPGA #verilog #vhdl

@azonenberg I haven't fully come to grips with my feelings about #GPL licensing, and corporate interests, etc.

I really wish I could do every bit of my designs completely in the open and release them completely in the open. I'm trying!

I like the viral nature of GPL in concept. But in practice it actually seems to make it harder for me to incorporate their code into my design even if I am releasing it under an open source license.

#foss #verilog #vhdl

Программируемый мастер шины I2C на FPGA

В данной статье я хочу рассказать про процесс разработки относительного простого модуля для ПЛИС (FPGA), а именно – контроллера (мастера) шины I2C. Он является ведущим устройством на шине. Я постараюсь показать последовательность всех этапов работ: проектирование, написание кода, моделирование и отладка в «железе». Статья в первую очередь ориентирована на тех, кто только начинает своё знакомство с ПЛИС. Надеюсь, она будет им полезна. Возможно и опытные разработчики смогут найти что-то новое для себя, увидеть интересные им идеи. В статье приводится большое количество исходных кодов контроллера (на языке VHDL) с их подробным разбором.

https://habr.com/ru/articles/943030/

#fpga #i2c #vhdl

"How do FPGAs execute blocking assignments in one clock cycle?"

Is the perfect question to frame common learning curve hurdles that folks need to get over when learning HDL.

https://www.reddit.com/r/FPGA/comments/1mcezqx/software_fpga_execution_a_pipelinec_response/

#fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda