[Перевод] Схемотехника стека сопроцессора Intel 8087 для чисел с плавающей запятой: реверс-инжиниринг

В 1980-м Intel 8087 превратил «плавающую точку» из мучения в рабочий инструмент для IBM PC — и заодно задал архитектурные решения, отголоски которых мы чувствуем до сих пор. В этой статье автор делает то, что обычно остаётся за пределами даташитов: вскрывает 8087, фотографирует кристалл и по слоям восстанавливает, как физически реализованы стековые регистры x87 и логика, которая двигает вершину стека, адресует ST(i) и ловит переполнения. Это разбор на уровне транзисторов, где дизайн ISA встречается с RC-задержками, SRAM-матрицами 8×80 и микрокодом, который реально «крутит» железо. Читать разбор

https://habr.com/ru/companies/otus/articles/980026/

#Intel_8087 #сопроцессор #x87 #микрокод #реверсинжиниринг #кристалл_микросхемы #схемотехника

Making all the difference in the world. #Valve #HalfLife #VR #compilers #x87 #SSE2 https://mastodon.gamedev.place/@TomF/115589904233959578

was doing some research on the once available 80bit FPU on #x86. otherwise known as #x87 instructions. The System V ABI and GCC actually stores them in 16 bytes with padded 0s. The #M68k , on the other hand, also features an 80bit floating point, has GCC store them in 12 bytes that fits into 3 32-bit registers.

#x87 #goroawase
i can't stop reading 80387 as Yamami Hana (山見 はな)

#x86 #x87

i've been reading some things on bus access for the 8087-80487 series of co-processors and the way that the bus is handed in the 8087 is different from the 287 and later.

for the 8087, the co-processor has DMA and takes control of the bus when it needs to do a memory access. i note that the 8087 doesn't calculate the initial address itself - the 8086 executes a dummy read cycle when it sees a co-processor instruction and the 8087 intercepts that address to use for it's DMA.
this means that the CPU has zero idea how the FPU executes instructions.

on the 287 and the 387, the CPU has complete control of the bus. the CPU tells the FPU what kind of cycle is on the bus (is this a bus opcode cycle, a bus memory read cycle, a bus memory write cycle), and the FPU only has control over the bus's data lines which it uses when given the opportunity to write to memory.
the FPU is completely oblivious to the state of the bus's address lines.
this means that the CPU must know what kinds of instructions the FPU is executing and must partially decode the opcode in order to know what requires a memory read/write.

you can see why they decided to just put the fpu on-die for the 486.

#x87 an operation on two QNaNs or SNaNs are documented to return the NaN with the bigger significand.

What if they have the same significant but different signs?
That's undocumented but testing looks like sign is 0 is returned unless both are 1 when the significands are equal.

#x87 unnormals round-trip as tbytes but become indefinites when converted

Why not push and pop ax a ton?

http://www.os2museum.com/wp/this-code-smells-of-desperation/

#x86 #x87 #windows31

PDF for William Kahan's Beastly Numbers paper:

https://people.eecs.berkeley.edu/~wkahan/tests/numbeast.pdf

"It seems unlikely that two computers, designed by different people 1800 miles apart, would be upset in the same way by the same two floating-point numbers 65535... and 4294967295... , but it has happened."

#postmortem #floatingpoint #x87 #cyrix

@esoterica

I updated a #haskell package:

https://hackage.haskell.org/package/long-double

An #FFI #binding to #C's #LongDouble #FloatingPoint #number #type. Traditionally on #x86 and #x86_64, long double has been an 80-bit #x87 type, and 32bit #ARM simply aliases to #double, but it seems #gcc on #aarch64 implements long double as #_Float128 which is #IEEE #quadruple #precision; so far tested only with #ghc and #gcc on #aarch64 (the functionality on other architectures should be unaffected).