Jay GateMateA1-EVB by Olimex arrived today. Too bad I have to do "grown up" things tomorrow.

#fpga #opensource #yosys #olimex

@adanskana
#ghdl, in its 5.0.1 llvm variant, is hosted in the electronics channel, and waiting to be merged in #guixscience channel (which provides guix substitutes), where it belongs, see

https://codeberg.org/guix-science/guix-science/pulls/87

The reason for not being part of #guix itself is its dependency on #gnat ada compiler, which cannot be bootstraped at this point. Remember we also have ghdl #lsp and the ghdl #yosys plugin.

The channel aggregator is here, by the way: https://toys.whereis.social/

Jeux de la vie sur fpga \o/

https://video.ploud.fr/w/ryoWzx42nJjaAsk3Rb2H8t

#gatemate #gatemateA1_evb #gameoflife #fpga #flf #yosys #openFPGALoader

Армения посреди Америки, Китая и России: отчет с EDA Connect 2025

Мысль, что Армения удобна тем, что соединяется и с Америкой, и с Китаем - высказал мне один из китайских участников конференции EDA Connect . А мысль, что Армения соединяется еще и с Россией - возникала естественно при просмотре докладов о логическом синтезаторе, статическом анализаторе и верификации с помощью UVM. Помимо докладов, при конференции прошел хакатон по Verilog и FPGA , на который пришли студенты из Ереванского университета, русско-армянского университета, американо-армянского, французско-армянского, европейско-армянского, и других университетов. Занятно, что второй день хакатона проходил в комнате напротив зала, где большое начальство встречалось с Премьер-Министром Армении. Один из студентов хакатона перепутал дверь, и его перенаправила секьюрити.

https://habr.com/ru/articles/891814/

#Армения #Synopsys #Mentor_Graphics #Verilog #SystemVerilog #Gowin #FPGA #Yosys #Utopia #UVM

Again, almost all the credit should go to @acqrel, she is the one who built the #yosys backend for this thing, I just took my existing core, removed all but 4 registers and programmed it

We had a very productive #FSD meeting earlier today! Check out what we accomplished: https://www.fsf.org/blogs/licensing/fsd-meeting-recap-2025-02-21 #FreeSoftware #Licensing #nextpnr #Yosys

\o/

Vive l'opensource,
vive le FPGA libre
vive l'europe ;)

🇪🇺

https://blog.yosyshq.com/p/an-open-source-fpga-toolchain-for-a-large-european-space-grade-fpga/

#yosys #europe #fpga #flf #nextpnr

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

@acqrel's #yosys backend for this thing works 👀🎉

Just got a 32-bit RISC-V SoC programmed into the Lattice ECP5 FPGA on Radiona's ULX3S using the completely open source LiteX toolchain, including yosys and nextpnr.

#fosh #foss #oshw #fpga #riscv #linux #litex #yosys #nextpnr

quick question about #verilog, or maybe more specifically #yosys: i've been messing around with an icebreaker fpga recently, and the ice40up5k chip has four banks of 32k x 8 bit spram built in. i wanted to use this ram in a design, but (either yosys or nextpnr, i'm not sure which is responsible for assigning hdl declarations to actual hardware) won't automatically assign things to this spram, so you have to manually work with it by instantiating a module of type `sb_spram256ka`. my question, then, is why yosys doesn't mind me using here a module that i haven't defined. since i've told it that i'm using an ice40 chip, is it just implicitly defining a bunch of modules?

The person who is porting #Yosys #NextPrN to #Gatemate on the #olimex board, is discussing his work on this Discord channel. #fpga #digitalmath #addition #multiplication #gaussianlogarithms.

https://discord.gg/gD3tCpbM

guix crash course

https://infosec.press/csantosb/guix-crash-course

Just purchased some new FPGA toys... An iCESugar and a pico-ice.

I'd like to finally play around with yosys and nextpnr. Looks like yosys is a bit old on Void, and there isn't a nextpnr package.

I'm half tempted to go through the effort of packaging these for Void Linux so others can benefit.
#FPGA #yosys #icesugar #pico_ice

Адаптация платы Colorlight 5A-75B для примеров «Школы синтеза цифровых схем»

Привет! Начался новый поток «Школы синтеза цифровых схем» и я хотел бы поделиться своим опытом по адаптации бюджетной платы с ПЛИС для запуска на ней лабораторных работ Школы. Отдельным преимуществом такого решения является возможность использования Open Source маршрута для синтеза и моделирования цифровых схем на базе Yosys и Icarus Verilog. Colorlight 5A-75B не является отладочной платой в привычном понимании этого понятия - будет интересно.

https://habr.com/ru/articles/849592/

#плис #fpga #yosys #lattice #verilog #systemverilog #icarus #gtkwave

With #guix, this is what it takes to produce a netlist for the 7 series of #xilinx #fpga devices.

> guix install yosys-clang ghdl-clang ghdl-yosys-plugin

> yosys -p 'ghdl --std=08 leds; synth_xilinx -top leds -family xc7 -ise'

It uses only #freesoftware, with #yosys and the #ghdl synthesis module as its backend.

Way too long since I last played with Verilog!

Also WHY OH WHY doesn't it seem to possible to access module parameters outside of the module (when not writing a test bench)... Would have been a nice way for some name spacing for constants.

Thanks to #yosys and #nextnpr btw.

@talpa Exactly :)

I'm waiting for NextPnR support now.
#gatemate #nextpnr #yosys

Working on my nixvim configuration, but also I have to setup a development environment for some open source FPGA tools.

Trying to figure out some of the open source FPGA tooling by setting breakpoints and running small demos. I need to figure out how the Surelog front end interacts with Yosys, for potential plugin development?

IDK, will write more about it later.

#fpga #yosys #nix #nixos #nixvim #neovim