#ICYMI you can now access the posters from #Spring2022RISCVWeek. The posters covered a range of topics from FPGA platforms to ML to vectors and more. View them all here: https://hubs.la/Q01b1Kfc0
Original tweet : https://twitter.com/risc_v/status/1524813489675681798
RT from SiFive (@SiFive)
At #Spring2022RISCVWeek, SiFive’s Perrine Peresse highlighted the benefits the #RISCV IOMMU specification will provide for virtualized systems. Stay tuned for the video! #NoLimits
https://twitter.com/FlorianWoh/status/1522189115118305280
Original tweet : https://twitter.com/SiFive/status/1524460580446380037
#DYK there are more than 12 billion #RISCV cores in the market?! RISC-V CTO @mark_riscv gave a state of the union at #Spring2022RISCVWeek to share updates from our technical work groups, including how we ratified 16 ISA specifications, consisting of 44 extensions, in 2021 alone.
Original tweet : https://twitter.com/risc_v/status/1523770029887610881
.@Andes_Tech’s @FlorianWoh highlighted how #RISCV “goes BIG” as we’re seeing more high-end RISC-V cores on the market, adoption of RISC-V is skyrocketing, and RISC-V is entering new markets. #Spring2022RISCVWeek #RISCVEverywhere
Original tweet : https://twitter.com/risc_v/status/1523046007034245120
“RISC-V empowers our community to seize growing opportunities.” At #Spring2022RISCVWeek, #RISCV CEO @Calista_Redmond discussed how RISC-V is enabling innovation across industries, including automotive, consumer IoT devices, AI/ML, edge computing, and HPC. #RISCVEverywhere
Original tweet : https://twitter.com/risc_v/status/1522724639511830530
RT from Gianluca Bellocchi (@GianBe_95)
Together with my poster (@UNIMORE_univ + @pulp_platform) at the #Spring2022RISCVWeek in #Paris! What an event! Many great people and exciting news from industry and academia have made this event a global success. No doubts: @risc_v is an inspiring and vibrant community to be in!
Original tweet : https://twitter.com/GianBe_95/status/1522515966168608769
RT from Sergio Mazzola (@mazzergio)
Super excited of having joined #Spring2022RISCVWeek with my poster. @risc_v has an amazing and energetic community, proud to be part of it! @pulp_platform
Original tweet : https://twitter.com/mazzergio/status/1522272126698500096
That's a wrap on #Spring2022RISCVWeek! Thank you for joining us for such a fun and packed few days of learning about #RISCV.
Original tweet : https://twitter.com/risc_v/status/1522229736684101632
This is the final call to attend the second poster session! Swing by the exhibition before it closes at 3:30 p.m. CEST (6:30 a.m. PT). #Spring2022RISCVWeek
Original tweet : https://twitter.com/risc_v/status/1522195655598518273
RT from Codasip (@Codasip)
“In a world where Dennard scaling & Moore's law is ending, you need to use architectural innovation to succeed”.
Zdeněk Přikryl presented at #Spring2022RISCVWeek
@risc_v
Download our latest whitepaper to learn how processor design is being redefined https://my.mtr.cool/zfuicmtqzs
Original tweet : https://twitter.com/Codasip/status/1521928101898428416
Interested in graph analytics on #RISCV GPU? Curious about using the TUM Uncore environment for RISC-V for teaching, #AI and quantum computing? Join our second poster session and exhibition to learn all this and more. #Spring2022RISCVWeek
Original tweet : https://twitter.com/risc_v/status/1522159164746780672
At 10 a.m. CEST (1 a.m. PT), #RISCV'S @mark_riscv and @VRULLEU's Philipp Tomsich will provide an overview of existing software and ongoing initiatives to enable adoption of RISC-V for ISVs, software distributions and system vendors. https://hubs.la/Q019wkgK0 #Spring2022RISCVWeek
Original tweet : https://twitter.com/risc_v/status/1522116383827533824
Join @VRULLEU founder Philipp Tomsich at 9:40 a.m. CEST (12:40 a.m. PT) for a presentation on key initiatives to create a robust ecosystem for ISVs while unlocking the benefits of #RISCV’s mix-and-match approach to ISA customization: https://hubs.la/Q019wm900 #Spring2022RISCVWeek
Original tweet : https://twitter.com/risc_v/status/1522108852904284162
Happy #RISCV International Day! It's the final day of #Spring2022RISCVWeek. We are kicking things off at 9 a.m. CEST (12 a.m. PT) with an exciting State of the Union address from #RISCV CTO @mark_riscv. Come hear about RISC-V's achievements and plans: https://hubs.la/Q019wklj0
Original tweet : https://twitter.com/risc_v/status/1522093733071753216
Day 2 of #Spring2022RISCVWeek has come to a close! Thank you to everyone for making it such an eventful day. We are excited to see everyone tomorrow for "RISC-V International Day" and the final day of our 3-day event.
Original tweet : https://twitter.com/risc_v/status/1521886115048927234
Wondering what's in store tomorrow at #Spring2022RISCVWeek? RISC-V CEO @Calista_Redmond run through tomorrow's exciting agenda at 6 p.m. CEST (9 a.m. PT).
Original tweet : https://twitter.com/risc_v/status/1521874790893694977
Curious about exploring #RISCV high performance compute clusters? Interested in hearing about composable custom extensions and function units for RISC-V? Come by the second #Spring2022RISCVWeek poster session to learn all this and more.
Original tweet : https://twitter.com/risc_v/status/1521848367265030146
Group is building #opensource, permissive, fully featured #RISCV IPs (called CORE-V). Join @DavideSchiavo10 at 2:30 p.m. CEST (5:30 a.m. PT) to learn more about the CORE-V roadmap and what's coming soon. https://hubs.la/Q019hkdf0 #Spring2022RISCVWeek
Original tweet : https://twitter.com/risc_v/status/1521821943246241793
#NaxRiscv is a recently developed OoO RV32/64 IMACSU softcore intended to provide better single threaded performances, keep logic resources usage reasonable, and more. Join @dolu1990 at 2:10 p.m. CEST (5:10 a.m. PT) to learn more. https://hubs.la/Q019hpQh0 #Spring2022RISCVWeek
Original tweet : https://twitter.com/risc_v/status/1521818169056370691
Attention, #Spring2022RISCVWeek attendees! The second poster session is in session. Come by to view all the informative #RISCV-related posters.
Original tweet : https://twitter.com/risc_v/status/1521791744827871232
