We found an Apple Silicon CPU issue with FJCVTZS, the "JS-compatible double-to-int32 conversion" instruction that was added to ARMv8.3.
If the Flush-to-Zero flag is set in the FPCR register and FJCVTZS is used with a denormal, my M1 sets the Zero flag to 1 and M2-M4 CPUs set it to 0. This flag indicates whether the conversion was exact. I believe M1 is correct?
Test case: https://gist.github.com/jandem/e6b5660975f145b85d533b97ad054f08