Two Weeks Until Tapeout
https://essenceia.github.io/projects/two_weeks_until_tapeout/
#ycombinator #asic #gf180 #180nm #rtl #verilog #JTAG #DFT #systolic_array #arithmetic

Playing with #GFMPW0 chips that I received from #Efabless with my test designs produced in #GF180 techprocess and fully paid by G ;)
And those chips are having decent RISC-V core inside :)

Today I am taping out another 5 chips, which takes me up to my 18th ASIC design!

2 chips are tests for the new #GF180 PDK.

Then #TinyTapeout 1 & 2, and a Zero to ASIC course submission. Between them they contain over 300 designs from hundreds of people around the world!