#rsicv

Banana Pi Open Source Hardwarebananapi
2025-03-07

Banana Pi BPI-F3 Risc-V SBC with SpacemiT K1 8 core RISC-V chip.
docs.banana-pi.org/en/BPI-F3/B

Banana Pi BPI-F3 Risc-V SBC with SpacemiT K1 8 core RISC-V chip.
https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3
#rsicv #bananapi #raspberrypi #aiot #ai #SpacemiT
Banana Pi Open Source Hardwarebananapi
2024-10-17
Banana Pi BPI-F3 RISC-V SBC  AI development documents.
https://developer.spacemit.com/documentation?token=R80owXgbkiwf34kWXyUcQOJDn5f
#sbc #rsicv #bananapi #SpacemiT #opensoruce #ai #aiot
2024-02-05

So the 18 by 18 bit multiplier went through the #gowin pack and the output was bits that were similar to the vendor version.
Tomorrow I'll check if it counts πŸ˜‰
Maybe for testing purposes it’s worth designing this #dsp as an external device to #rsicv? It would be funny and I would be able to immediately see the result in the terminal via UART, and not on LEDs, of which, by the way, #tangnano4k has only one.
#apicula #sipeed

Terminal. Design build log using #yosys - #nexpnr - #gowin-pack.
Part of the routing is visible and, most importantly, the generated bits for the multiplier.
2024-01-20

Now that #apicula has a mechanism for BRAM inferring (yay!) I can move on with this tutorial for the dumbest (that is, me) "Make your #rsicv on #fpga"πŸ˜‰
I immediately ran into the following obstacle: #tangnano9k has some of its own ideas about how to react to the external clock signal GCLKT_4 (in my case, not at all). Looks like we have an implicit wire here, I'll try to find it.

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