Lmst

Two word vs byte addressing bugs were cancelling each other out. The life of the hardware developer! 😬 #FPGA

High Performance Image Sensor Processing Using FPGA [pdf]

https://oda.uni-obuda.hu/bitstream/handle/20.500.14044/10350/Gabor_S_Becker_ertekezes.pdf

#HackerNews #HighPerformanceImageSensor #FPGA #ImageProcessing #Technology #Innovation

Fitting in some #FPGA time on a Sunday during poor weather. I'm making my canvas (bitmap) addressing modules for display and drawing consistent and 32-bit ready. Strangely satisfying to do this routine stuff sometimes.

🌘 開源 FPGA 網路專案：教育版
➤ 開放網路的未來：FPGA 驅動的教育創新
✤ https://privateisland.tech/betsy
Private Island Networks Inc. 宣佈將贊助並支持2025/2026學年度的大學專案，這些專案將利用其開源網路堆疊（Private Island®）和Betsy™製作板，專注於網路安全、隱私及機器學習等領域。該專案旨在提供一個開放、可信任且可擴展的封包處理與安全系統，並鼓勵學生探索創新應用，包括異常網路活動偵測、安全通訊和威脅建模等。
+ "這個計畫太棒了！讓學生能實際操作硬體，深入瞭解網路安全，比單純的理論學習更有價值。"
+ "開源的特性讓人感到興奮，可以自由地修改和擴展，相信會有許多有趣的應用出現。"
#開源硬件 #網路安全 #FPGA #教育

Parallelizing SHA256 Calculation on FPGA

Link: https://www.controlpaths.com/2025/06/29/parallelizing_sha256-calculation-fpga/
Discussion: https://news.ycombinator.com/item?id=44456027

#fpga

Parallelizing SHA256 Calculation on FPGA

https://www.controlpaths.com/2025/06/29/parallelizing_sha256-calculation-fpga/

#HackerNews #Parallelizing #SHA256 #FPGA #Technology #Cryptography #HardwareAcceleration

Wait… the Sega Neptune is actually happening?!
Coming this December as an FPGA console, and it plays both Genesis and 32X carts. After being canceled decades ago, this thing's finally real. Wild.
Retro heads, you already know what time it is.
#SegaNeptune #RetroGaming #FPGA

Monochrome 672x384 image on @machdyne Lakritz #FPGA computer (ECP5).

Lakritz FPGA computer in black 3D-printed case driving a display. The display is showing a monochrome image of crocuses. The display information shows the display mode is 1366x768.

Time to test out packed monochrome images on my #FPGA graphics hardware. This is a 672x384 monochrome version of the crocus photo I've been using. Yes, it is Floyd–Steinberg dithering.

Monchrome image of crocuses with Floyd–Steinberg dithering.

turboerer

#zeST #Atari #AtariST #FPGA #retrocomputing

btw, turboer

#zeST #atari #atariST #FPGA #retrocomputing

Cute little open source FPGA board made by machdyne. The company is located about half an hour from Bamberg… nice!

#FPGA #Lattice #machdyne #openhardware

Lattice FPGA board with 32 MB SDRAM, VGA, SD, USB and a PMod connector.

This gibberish is me getting a simulation of the SDRAM chip used on the ULX3S working under a testbench. My goal is to write a very simple UART->SDRAM->UART dataflow and I was having data corruption issues that were (for beginner me) hard to track down. Now I can use the chip simulation to write some better code and hopefully get everything writing correctly. #fpga

Graph of signals. At the top for two related to a simulated UART showing data inputs. Next are several signals showing SDRAM write request and completion status as well as the data to write. Finally, some signals related to the commands requested of the SDRAM and the internal state of the SDRAM controller I'm using.

🌘 微晶片可配置邏輯區塊 (CLB) 反向工程：解構微晶片 CLB 內部
➤ 自力解構，掌握 CLB 真面目
✤ http://mcp-clb.markomo.me/
這篇文章記錄了一位工程師對微晶片 (Microchip) PIC16F13145 微控制器的可配置邏輯區塊 (CLB) 進行反向工程的過程。微晶片在其新系列的微控制器中加入了 CLB，這是一個相當於小型 FPGA (32 個 LUT) 的功能，可以直接連接到晶片的內部。然而，微晶片僅提供線上配置工具，未公開 CLB 的配置細節。因此，作者決定自行反向工程 CLB，並將過程分為背景介紹、硬體測試和實作三個部分。
+ 終於有人願意研究這個神祕的 CLB 了！微晶片的作法實在太封閉了。
+ 這份反向工程的紀錄對想深入瞭解 CLB 運作原理的人來說非常有幫助，期待後續的實作分享！
#微電子 #反向工程 #FPGA #微控制器

#BrightEyesTTM: #OpenSource #FPGA-based multi-channel time-tagging module (#TTM) for democratising single-photon (SP) #microscopy:

-parallel multiple #SP event tagging precision: 30 ps
-multiple synchronisation event precision: 4 ns
-requires #LabVIEW
-cost ~$3000

Article: https://doi.org/10.1038/s41467-022-35064-0
Web: https://brighteyes-ttm.readthedocs.io/en/latest/
GitHub: https://github.com/VicidominiLab/BrightEyes-TTM
#DIYbio #lab #instruments #LSM #FLISM #FLFS #fluorescence #spectroscopy #imaging #Python

Wenn Licht doch nur 396.322.730 Kilometer pro Sekunde zurücklegen würde hätte der Tag 65.536 Sekunden und ich könnte einen 16 Bit-Counter dafür nehmen …

Aber nö, es sind bloß 299.792.458 und deshalb braucht eins 17 Bit und davon werden auch noch 0,6 verschwendet.

#FPGA

🌕 如何在自製 CPU 上運行類 Unix 作業系統 (Xv6) 及使用自製 C 編譯器
➤ 從 CPU 設計到作業系統移植：一場大學生的硬體與軟體冒險
✤ https://fuel.edby.coffee/posts/how-we-ported-xv6-os-to-a-home-built-cpu-with-a-home-built-c-compiler/
這篇文章詳細記錄了作者及其團隊在大學期間，如何設計自有指令集架構 (ISA)、使用 FPGA 構建處理器、開發 C 編譯器，並最終成功將類 Unix 作業系統 Xv6 移植到該自製 CPU 上的過程。這個專案源於東京大學的「CPU 實驗」，團隊不僅克服了編譯器、CPU 功能、模擬器和程式碼可攜性等多重挑戰，更在原本的實驗基礎上，透過團隊合作，實現了運行作業系統的目標，展現了高度的學習能力和創造力。
+ 令人驚嘆的專案！能把整個作業系統跑在自己設計的CPU上，真的是非常厲害的成就，也證明瞭理論與實作結合的重要性。
+ 這篇文章寫得真詳細，讓人對整個專案的過程有很清晰的瞭解。感覺這
#硬體 #軟體 #作業系統 #編譯器 #FPGA

My latest blog post: Trying out the ice4pi from Lightside Instruments

https://mikecoats.com/ice4pi/

At the recent @oshwassociation Open Hardware Summit, I was lucky enough to run in to Vladimir from Lightside Instruments. He was kind enough to gift me one of their ice4pi iCE40 shields.

#electronics #fpga #ohs2025 #openHardware #openSource

Has anyone created a Lattice ECP5 #FPGA dev board with an LVDS connection for direct attachment to an LCD panel? This would save the cost and complexity of converting to TMDS and back again. I have a Pimoroni driver board (pictured), but the ECP5 can generate LVDS signals directly.

ULX3S FPGA dev board connected to 1024x768 LCD panel via TMDS to LVDS driver board. The LCD panel is displaying "FLUX FPGA EARTHRISE" in an angular font.

Another Lakritz #FPGA dev board test. 336x192 16-colour crocus test image at 4x scale.

1366x768 was a ubiquitous laptop resolution for many years. I hope my project will help find a purpose for unused LCD panels. #permacomputing

#fpga

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