The probability of @tnt in a presentation is low, but it's never zero!
Matthias Jung presenting on ASIC design
#tinytapeout
60,000:1 CMOS inverter scale model - now with magnets!
Get his little brother at the #TinyTapeout store:
https://store.tinytapeout.com/products/Sky130-Inverter-Model-Kit-p727081769
Streaming on open source silicon in 3 hours!
I'll be looking at the results of the #TinyTapeout survey, and picking a winner for the wafer prize.
Then Pat Deegan will be joining me to talk about putting our ASICs in Space!
https://www.youtube.com/watch?v=SgO8fle5yrw&ab_channel=ZeroToASICCourse
Testing Ricardo Nunes's 12 bit SAR ADC on #TinyTapeout 7!
Til aftenkursus hos IDA: Introduction to Open-Source Chip Design and Tiny Tape out #chipdesign #tinytapeout
Combining semiconductors with music for my @hackaday Berlin lightning talk - check out this exciting Tiny Tapeout update!
A friend points out that @tnt is live, and trying out his silicon design he got out of the last #tinytapeout delivery.
https://www.youtube.com/live/indh938493w
Instant device bench envy!
Hacking together my submission for the next #tinytapeout ... the circuit works, but could use a bit of cleanup :-) Thanks @matthewvenn for the excellent workshop!
Oh no! Efabless has shut down. Terrible news for #tinytapeout
https://docs.google.com/document/d/12KPutDPBst7FF0ncB1qyxErDYeATmXoQLGjRq38dfjU/mobilebasic
Had some fun testing Ricardo Nunes's 12bit SAR ADC on #TinyTapeout 7 this afternoon.
A SAR ADC is a nice mixed signal example, with the digital section coordinating the binary search of an internal DAC, homing in on the input signal.
Glad I could test it myself and see it working!
@matthewvenn It was so unexpected and sad. It's obviously far too soon to speculate on what happens now and what's in future for #tinytapeout, but I hope something will rise from the ashes.
@wren6991 I completely agree and capacities are meager. I'm really eager to see this realized. IO count ~ 5 + max(DQwidth, ADwidth), say 21? Could almost work with #Tinytapeout
Last few days for Tiny Tapeout 10!
The shuttle closes at 21:00 CET / 12:00 PT on Monday 10th of March.
We have some great projects on board already, including 3.3v mixed signal analog, a bandgap reference, the demoscene competition entries and RISCV SoCs.
But we want even more, so put on your ASIC hat and get that last minute design submitted onto Tiny Tapeout 10!
Tapeout as a handicraft seems to have died out not long after there were computers "bootstrapped" for CAD. It's pretty eye-opening to look back on the early history of integrated circuits now: jocelynhyt8 on Instagram has made an incredible reproduction of some MOS 6502 masks that give a sense of complexity:
https://www.instagram.com/jocelynhyt8/p/DBHoI6-PYzO/
Here's an era-appropriate MOS SRAM mask to compare:
https://www.computerhistory.org/revolution/digital-logic/12/287/1609
I wonder if any hobbyists have tried something like this for #tinytapeout?
Tiny Tapeout 10 demoscene competition is open! Enter for free and win some great prizes!
https://tinytapeout.com/competitions/demoscene-tt10/
Don't miss my next open source silicon stream!
As well as the latest news and events I'll be looking at some new silicon proven designs and look at reading and writing via SPI.
This is the QSPI clock being output from my TinyQV design on #TinyTapeout 06.
It's a 32MHz clock, which should be within spec of the Tiny Tapeout outputs, which are rated to 33MHz.
As you can see, a couple of the clocks are rather low. This does just about work, but definitely warranted further investigation!
"Tiny Tapeout is an educational project that makes it easier and cheaper than ever to get your designs manufactured on a real chip!"
In the video above, it is acting as an 8 bit shift register with feedback, so in theory, we could build another layer now :D
I also did a time multiplexed nand gate on #tinytapeout 4, but then I didn't have the shift registers so I could only fit 128 bits of state compared to the 880 (in 2 tiles) here.
Of course, the tradeoff is time. Me and a friend think we will be able to fit an RV16I on this, but it will run at literal HZ with the ASIC clocked at MHz
What is it you may ask? It is a time multiplexed NAND-gate and a giant shift register. Schematically, it looks like this.
Every clock cycle, it can read a value from the top of the shift reg to either the left or right operand, and write an input or the current NAND output back into the shift register.
This is able to emulate any circuit with <880 bits of state+wires, but it won't be fun to program, nor fast.
Client Info
Server: https://mastodon.social
Version: 2025.04
Repository: https://github.com/cyevgeniy/lmst