Commander X16 65C02 Assembly Tutorial – Episode 1
#CommanderX16 #AssemblyLanguage #WDC6502 #RetroComputing #X16Tutorial
https://theoasisbbs.com/commander-x16-65c02-assembly-tutorial-episode-1/?feed_id=3404&_unique_id=682c7fb238dd3

"The Apple IIGS Megahertz Myth", why the IIGS only runs at 2.8MHz and the history of the 65816 CPU.

https://www.userlandia.com/home/iigs-mhz-myth

#wdc6502 #mos6502 #retrocomputing

I have updated the 6502 Instruction Set Database I made a couple of weeks ago:

https://gitlab.com/Screwtapello/isa65xx

New in this version:

- Now has all the instructions, addressing modes and cycle timings of the 65C02 (the base model, not including extensions added by Rockwell and WDC)
- Represents instructions with the same mnemonic but different behaviour, like the way BIT's immediate mode is different from the others, and indirect JMP is more like an instruction than an addressing mode
- Represents the number of potential extra cycles for each instruction, in addition to the minimum cycle count

As usual, the thing I'm most proud of is the citations and explanations - over 50% of the source file is comments! If you're learning about the 6502 and want something more verifiable than bare assertions on a random website, take a look!

#retrocomputing #mos6502 #WDC6502

Trying to educate myself about the #WDC6502 (well, the 65C02).

"JMP $1234" takes three cycles: one to read the opcode, and two to read the target address from the instruction.

"JMP ($1234)" takes six cycles (on the 65C02): one to read the opcode, two to read the pointer address from the instruction, two to read the target address from the pointer, and "an extra cycle making sure the high byte of the indirect address is correct (this fixes the famous 6502 indirect jump bug)."

"LDA $1234" takes four cycles: one for the opcode, two to read the target address from the instruction, one to read a value from the target address.

"LDA $1234,X" takes four or five cycles: as above, but if adding the X register to the address crosses $xxFF, it takes an extra cycle to add the carry bit to the high byte of the resulting address.

"JMP ($1234,X)" should therefore (to my mind) take six or seven cycles: one for the opcode, two for the pointer base address, an optional cycle if indexing crosses a page boundary, two for the target address, and the extra "fix the indirect jump bug" cycle.

However, every reliable reference I can find insists that it's always and only six cycles, it never pays the page-boundary-crossing penalty. Every other instruction optionally or *always* pays the penalty. I don't see why this one instruction should be different.

What am I missing?

#retrocomputing #mos6502

I decided I wanted to learn more about the instruction set of the 6502 microprocessor. As Douglas Adams wrote, "By the time you’ve sorted out a complicated idea into little steps that even a stupid machine can deal with, you’ve certainly learned something about it yourself." And so I set out to explain it to SQLite, to verify that I understood it correctly.

https://gitlab.com/Screwtapello/isa65xx

#retrocomputing #mos6502 #WDC6502 #assembly

Wild question, does anyone know of a 65C02 variant -- and the reset vector at FFFE/FFFF?
I'm poking around in the General Instrument MVP scrambler firmware and the code seems to be vaguely passable if fed through a 6502 disassembler, aside from some instructions which are undefined on the WDC 65C02S.
#RetroComputing #analogcable #MOS6502 #wdc6502