Attended "An Open Source RISC-V CPU in FPGA" by Kristoffer Robin Stokke at UiO. Pure OS joy!
- 32-bit `RISC-V` CPU in open `VHDL` on a cheap FPGA
- Minimalist: UART, SDRAM, pixel screen
- All source code open
Saw the FPGA board IRL—tiny silicon, big dreams. Bare-metal computing distilled. Trying to convince Kristoffer to present this at FOSDEM!











