Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

Playing with #litex #litescope FPGA logic analyzer. That stuff works super well. What the #FOSS #fpga people (#litex #migen #oss-cad #yosys #openocd and all the others hidden in the toolchain) have done is amazing. The board is a colorlight 5a-75b with an ECP5.
https://kraut.zone/w/k2qy5PXbBuHhozcDf9QgbP

Code: https://github.com/bjonnh/alscope

The differences between #migen and #nmigen are reminiscent of the differences between Chisel 2.0 and Chisel 3.0.

After asking about #Migen contributions, I've basically been recruited into contributing to the #nmigen project instead. :)

Hmm, the tutorials for #Migen are dated (read: broken). But, after much searching around, I was able to work around the deficiencies in the tutorials.

I'm thinking I should create a PR for the project and submit a new tutorial to replace the old tutorial with updated installation instructions and import paths.

Looking at the sources for the KCP53000 processor that I used with the Kestrel-2DX, there's just a ton of lines of code that I'd need to fix to get reliable synthesis with yosys. Plus, I'd need to write Furcula to TileLink adapters, prove them separately, etc. Yuck.

I think it'll be better if I start from a clean slate.

Maybe now would be a good time to learn how to use #Migen.

#migen question: how can i get, for instance, pin one of the PMOD connector, without writing up _io defs?

/cc @cr1901