Lmst

Look at what I've just received from Digikey :)

#FPGA #SucreLA #openhw #osh

It's already Xmas! 🎄

plastic tray containing 4 Lattice ECP5 FPGAs in TQ144 package

Paper showing humidity detection of the shipping + the silicate humidity absorber.

PSA: This just landed on my work feed:

Zynq UltraScale+ Design Advisory

https://adaptivesupport.amd.com/s/article/72992?language=en_US

#FPGA #Xilinx #vhdl #verilog #pcie

Hey Digital Working Group,
I just got burned by a defect in the ZU when using it as the PCIE endpoint. You cannot boot the ZU until there is a valid PCIE clock (100MHz) at the GTR REFCLK inputs.

This would not have been a problem if I could have used a common clock reference to the NVIDIA SOM and ZU. But the SOM does not support a common clock input. It only provides a PCIE clock, so I'm left with connecting the SOM PCIE_REFCLK output to the ZU GTR REFCLK input. This means I now have a race condition between the ZU booting and the SOM booting. I have to hold off the ZU booting until the SOM is providing that clock reference.

Here's the design advisory:
https://adaptivesupport.amd.com/s/article/72992?language=en_US

Be sure to read all the way to the bottom!

Additional System Considerations:
For all systems using SATA or PCIe, the GT Ref Clock must be present and stable from the beginning of the boot process.
This can have a similar failure mechanism to the issue described above. This requirement should also be checked.
Link failures can be observed with and without the patch if this requirement is not met.
If your system cannot meet this requirement, please contact support.

Isle.Computer hardware text mode on #ULX3S. With 2x scaling and horizontal offset to centre at 1366x768. I’m getting ready to release the next chapter and hardware designs. #FPGA

ULX3S FPGA dev board connected to widescreen monitor showing test text 16 colours.

Are you working at the intersection of languages and tools for accelerator design? Then you should submit a paper to our workshop, LATTE ☕

As usual, it is a hybrid workshop co-located with ASPLOS which is in Pittsburgh this year. You can join remotely, or in person!

CFP: https://capra.cs.cornell.edu/latte26/
Deadline: Jan 31
Workshop: March 22/23

#fpga #asic

A rectangular image with the text LATTE '26 in large brown font, and be low that "Workshop on Languages, Tools, and Techniques for Accelerator Design"

On the left side there is a stylized cup of latte

Au fait, Même si la couverture n'a pas changée, le livre «Digital Design with Chisel» en est déjà à sa 6ème édition depuis 2019.

https://www.amazon.fr/Digital-Design-Chisel-Martin-Schoeberl/dp/168933603X

C'est amazon (print) :(
Est-ce que c'est mieux que du bolloré ou lvmh ?

#chisel #flf #fpga #verilog #électronique #scala

Deux livres Digital Design with Chisel avec exactement la même couverture mais le second est beaucoup plus épais

hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware

#FPGA #HLS #MachineLearning #ML #DeepLearning #DL #Package

https://hgpu.org/?p=30438

Der Wunsch Spiele Stream XX startet in wenigen Minuten. Es ist der letzte für dieses Jahr und die Zuschauer haben sämtliche Kosten und Mühen gescheut... #twitch #stream #retro #mister #fpga #wdw #wunschspielestreaam

Isle text mode hardware supports separate X and Y scaling. #FPGA

Text mode with x-scale=1 and y-scale=1 in Verilator/SDL simulation. 84x24 half-width glyphs.

Text mode with x-scale=3 and y-scale=2 in Verilator/SDL simulation. 28x12 half-width glyphs.

Text mode with x-scale=6 and y-scale=4 in Verilator/SDL simulation. 14x6 half-width glyphs.

@RueNahcMohr Well, now that the #fpga has stopped overheating, I think I'll start my annual search for a programme for drawing diagrams with elements such as LUTs, various types of digital flip-flops, and wires between them.

As usual, it will end up being either Inkscape or paper and pen.🤣

https://hdlbits.01xz.net/wiki/Main_Page has been a really wonderful intro to Verilog HDL. I love their use of language that has helped me think about Verilog as not quite programming (at least as I've thought of it from a software standpoint so far). Staying focused on the hardware, the signals, the wires "driving" 1s & 0s around has been fantastic for getting my brain to settle in quickly to this new way of thinking. Highly recommend!
#verilog #FPGA

So I guess this de-emphasis control reg is what I want on the TMDS181. But, it says it only works for retimer mode, and I’m running at ~900 MHz right now, so too slow. It operates in redriver mode here.

Maybe the TX swing control? Not sure.

#fpga #oscilloscope #electronics

Register map and description for the TMDS181 with HDMI_TWPST0 highlighted

Finally, I have achieved a normal temperature for this GW5A series chip!😀

Until now, the board would easily reach 50 degrees in a matter of seconds, which clearly indicated a problem.

I had to select many bits by touch in the IO blocks, including banks and unused pins.

Now I can move on to LUTs and clocks as usual without documentation.😜 #fpga#apicula#gowin#sipeed

The thermal imager shows that the TangMega138k is heating up to ~33 degrees.

I finally soldered my D420-A 4 GHz probe onto the SoundSlab's HDMI input. After learning the UI a bit, my LeCroy SDA 760Zi is triggering on HDMI control symbols and producing an eye diagram.

That looks a lot like overemphasis to me, but I’m not an expert here at all…

This board has a TMDS181 retimer in front of the Artix GTPs with registers to adjust things that I haven't played with yet. Now that I can see what I'm doing, maybe it's time!

#fpga #oscilloscope #electronics

LeCroy D420-A probe soldered to coupling capacitors on HDMI lane 0 of the SoundSlab’s video board

Eye diagram and trace from the LeCroy scope showing what I think is overemphasis

Xilinx AXI DMA v7.1 (Simple Mode)

Я заметил, что в сообществе FPGA многие задают вопросы, которые можно решить с помощью DMA. Сделал поиск по Хабру в поисках чистых статей о том, как запустить DMA и не нашел таких. Поэтому решил в этой статье собрать свои знания в кучу и показать, как пользуюсь DMA . Это будут чистые примеры, без лишней информации, также будут сравнительные тесты разного характера.

https://habr.com/ru/articles/974008/

#FPGA #MicroBlaze #Vivado #DMA

:neofox_sign_aaa: iceprog pushed the binary to the board. Annnd the LEDs blink now! :blobfoxwhoaa: Pretty!
#FPGA #alhambraII #ice40

fedi #fpga crowd: What’s your opinion on Xilinx Spartan Ultrascale+ versus either Artix 7 or Lattice ECP5 regarding PCB implementation complexity and usability of their logic resources?

OMG OMG OMG AXI DMA works :D

#FPGA #DMA #AXI #Beagle-V-Fire #RISC-V

Screenshot of a terminal on a device names "klee" showing the following commands:

echo -n a | sudo tee /dev/udmabuf-fun
a

cat /sys/class/u-dma-buf/udmabuf-fun/phys_addr
0x00000000c4000000

sudo devmem2 0x45000070 w 0xc4000000
/dev/mem opened.
Memory mapped at address 0x3fb3b27000.
Value at address 0x45000070 (0x3fb3b27070): 0x0
Written 0xC4000000; readback 0xC4000000

sudo devmem2 0x45000074 w
/dev/mem opened.
Memory mapped at address 0x3fb981e000.
Value at address 0x45000074 (0x3fb981e074): 0x61

mmm... FDTI driver issues it seems, but I know I installed the ftdi package? Can't find iCE FTDI USB device. Maybe permissions?

Yep! Needed to add my user to the tty group (like dialout group on ubuntu) for /dev/ttyUSB* on Void Linux.

This article was helpful: https://linuxvox.com/blog/reading-and-writing-to-serial-port-in-c-on-linux/ #FPGA #openSource #alhambraII #ice40

Step 1 is Software to talk to this thing I guess. Gotta get the Yosys, NextPNR & IceStorm tools installed it seems. ✅ #FPGA #openSource #alhambraII #ice40

Determined to figure out this FPGA thingy that's been sitting in my desk drawer for almost a year now... :determineline: I have a datasheet. Let's go! #FPGA #openSource #alhambraII #ice40

#FPGA

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