I received an #upduino and a #picoice circuit board this week, got the basic tools working, and am working on an echo server. Soon I will be building a #Mecrisp #Forth core.

I am giving a talk on #Forth this week at the #fpgaworld conference in stockholm.
#fpga

#ZeptoForth boots on the #PicoIce, which means that the default power, usb and flash pins are correctly connected. Which means that #MicroPython and #Mecrisp probably boot as well.

As soon as I get my #FPGA working on the #Upduino, I want to buy a Pico-Ice, and check out the REPLs..

I bought the #upduino board. $33 List Price. $97 shipped to Europe and taxed. And I still need some #pmods.

Now I feel like goofing off until it arrives.

#forth #mecrisp #manycore #transputer #csp

I will be using th #Upduino board, not the #PicIce board. So much simpler, and it optionally comes with 4 pre-doldered headers (slots) for #pmods.

There is even a version of #Mecrisp which already runs on the Upduino.

And I can do all the development on my Mac!

I am building a many core #Forth processor on Lattice Semiconductor FPGAs using the open source #Yosys tools. The first products released will be two 4 core processors. 16K* 16 bit words or 10.6K * 24 bit words. Every pair of processors will communicate using 10Kbits of dual port RAM. The processors will run on the $35 #PicoIce and $30 #Upduino boards. Later there will be hundreds of cores on the larger #ULX3S #ECP5 boards.

My climate persona: @UncensoredNews
#fpga #ManyCore #introduction

@tedchoward

Whoa!

PORT CRYSIS, OBVIOUSLY!!! 😆

Better yet, port #uxn.

It's a porter's dream, and I think it will become a big hit with the retro community.

#retrocomputing #fpga #upduino

Ok. I have a very basic 40 column text mode working using the uart for input. I’m trying to decide what my next step should be.

#Retrocomputing #fpga #upduino

This is my #upduino #fpga based video processor for my homebrew computer being controlled by an Arduino.

Progress!

#retrocomputing

Ok, I’m making progress. Some tweaks to the DAC (thanks @mos_8502 and @andreasbombe ), but the thing that made the most difference is something stupid I was doing.

When I wrote the #verilog to generate the test pattern, I neglected to include the blanking interval in the output. Adding that instantly made the colors brighter!

Still a lot to do, but progress continues!

#retrocomputing #fpga #upduino

Well, I’ve got colors. Although, not the colors I want. The “white” is very yellow. They are all very dim. And I have these vertical bars appearing as well. Not sure what’s causing that.

#Retrocomputing #fpga #upduino

Resistor DACs are “fun”.

#Retrocomputing #fpga #upduino

Tonight I:
- soldered header pins onto the #upduino
- wrote some simple verilog to generate VGA sync pulses
- wrote some more verilog to write numbers (b&w only)
- wired this thing up to a monitor

This was a productive evening.

#retrocomputing #fpga #upduino