GateMate DVI out.
1080P (1920×1080) @60 FPS on the #GateMate #FPGA using the TI TFP410.
He does 2 pixels per clock internally at ~74.25 Mhz, externally uses DDR at 148.5 MHz
https://elektronaut.tech/en/fpga/driving-full-hd-video-with-the-cologne-chip-gatemate-fpga/
@xcabal05
I am interested in #LibreRouter technology.
The European made #GateMate #FPGA has a #5Gbps #Serdes. I can use it to do #UDP #camera in and display out. So I am just learning about the internet protocol, starting with voltages.
Which Open Source UDP library should I be using? is there one you recommend in Verilog?
There is now a github repository to compare the performance of FPGAs. The repository contains test cases for adders, counters and muxes. Now we know how much faster GateMate is than ICE40.
Fully #freesoftware based support for GateMate FPGAs from Cologne Chip [0] just landed in #guix.
It includes #yosys for synthesis, #openFPGALoader for device flashing and #nextpnr for placement and routing.
guix shell -C -m manifest.scm -- make
The whole toolchain runs in a #sourcehut #ci pipeline.
https://builds.sr.ht/~csantosb/job/1588460#task-test
[0] https://indico.cern.ch/event/1587509 for details on #gatemate #fpga.
https://indico.cern.ch/event/1587509/#3-introduction
Today the #CERN 's #FPGA Developer Forum will host a seminar by Patrick Urban from #CologneChip with the title " #GateMate : a #European 28nm FPGA with an #OpenSource toolchain and radiation qualification results". The event will start at 4pm CET, there is a zoom link to follow from the remote!
Thank you @BalCCon it was again amazing experiences to be part of this super cool conference! This year I have talked about new #ULX5M board that is hosting #EU #CologneChip #GateMate chip, held small talk about #RadionaORG #ZigZag badge and had #Assembly where it was possible to assemble personalized badge!
As I did not post for a long time I will start from an end. We got #ULX5M-GS up and running!!! #CM5 pin compatible #FPGA #SoM with #EU Cologne #GateMate A1 and fully open source toolchain. Still lots of work left, but I am really happy to see DVI out!
Uhhh nice #aisler can source components without requiring that you use them for assembly.
Might be a way to share the cost of having VAT declared and also the shipping from lcsc.com.
Lets create a small test "blinkenlichts" board for my #gatemate, I could use one anyway.
They can't find the
FH-00088 (stock 920) oh well, DS1023-2*10SF11 will do just fine. Hey the system found those... claims they are not in stock (1715)?
Worse still LEDs and resistors €87, just nope, not going to happen!
Happiness is a git pull and rebuild of #nextpnr / #prjpeppercorn
Not only does "placer2" now work for me (it is a lot faster than "placer1")
But best of all my #gatemate memory mapped SPI interface now works!
"Wiggle your SPI lines in excitement" as a space invader would say.
Thanks to everyone and according to git logs for prjpeppercorn, a special thanks to Miodrag Milanovic
I give up! (for now)
Does the Masterdon network know why I can't control any of the SPI configuration flash pins on my #olimex #gatemate evaluation board?
From the .ccf file:
Pin_out "spiClk" Loc = "IO_WA_B8";
Pin_out "spiCs" Loc = "IO_WA_A8";
Pin_out "spiMosi" Loc = "IO_WA_B7";
Pin_in "spiMiso" Loc = "IO_WA_A7";
And the synth log indicates that yosys mapped the correct primitives to the pins
Mapping port top.spiClk using CC_OBUF.
Mapping port top.spiMiso using CC_IBUF.
Initial impressions of the #olimex #gatemate
The good:
* Very nice with another open toolchain FPGA board.
* Open source hardware
* Build in programmer and UART interface
* Almost all the tools for programming the board is available in Debian unstable
The bad:
* The Olimex supplied documentation is very very minimal, almost non existing
Nitpicks:
I have yet to find a way for resetting though JTAG_RST.
As a result I currently have to press the button for consistent programming success.
Tiny Shader running on the GateMateA1-EVB with an open source toolchain 🎉
Originally this design was created for Tiny Tapeout, more information can be found here: https://github.com/mole99/tt06-tiny-shader
And if you want to see the TT06 chip in action, take a look at this thread: https://fosstodon.org/@mole99/113730908871370284
I've got myself a new toy 🙌
This is the GateMateA1-EVB from Olimex, an FPGA dev board containing the GateMate CCGM1A1 with 20480 CPEs.
Now that initial nextpnr support for the chip has been merged, it is possible to program it with a fully open source toolchain 🎉
Synthesis with Yosys, place and route with nextpnr, bitstream packing with gmpack and finally upload to the board with openFPGALoader!
That meant I just had to get one, and two days later it arrived!
Jeux de la vie sur fpga \o/
https://video.ploud.fr/w/ryoWzx42nJjaAsk3Rb2H8t
#gatemate #gatemateA1_evb #gameoflife #fpga #flf #yosys #openFPGALoader
I am so glad to report that Cologne Chip will be sponsoring the CERN 2025 FPGA conference. The email announcement just arrived.
Very motivating.
https://indico.cern.ch/event/1467417/
@AlgoCompSynth
Mecrisp Ice has a couple of 32 bit soft core stack machines, but I have not paid close attention to them. Music is fine with 16 bits. Real world control is usually at 20-22 bits. Video is 24 bits. FPGA real estate is both expensive, and slows things, so not much reason to go beyond 24 bits. Sadly I do not know of any fpgA with 24 bit memory. #GateMate has 20 bit memory, on a $50 board. Most interesting;
