Lmst

How the Sun Enterprise 10000 was born (2007)

https://www.filibeto.org/aduritz/truetrue/e10000/how-e10k-wasborn.html

#HackerNews #SunEnterprise10000 #Sun #Microsystems #TechHistory #ComputerArchitecture #Innovation #2007

Reverse engineering the 386 processor's prefetch queue circuitry

http://www.righto.com/2025/05/386-prefetch-circuitry-reverse-engineered.html

#HackerNews #ReverseEngineering #386Processor #PrefetchQueue #Circuitry #TechHistory #ComputerArchitecture #HardwareHacking

Load-Store Conflicts

https://zeux.io/2025/05/03/load-store-conflicts/

#HackerNews #LoadStoreConflicts #MemoryManagement #ComputerArchitecture #ProgrammingInsights #TechTrends

On April 2, 1997, AMD released a new CPU. If it succeeded, AMD had a chance at success. If it failed, AMD would probably fail with it. That CPU was the K6, and it revitalized AMD, letting them move to the middle of the market, where margins were high enough to fund its future CPUs. #RetroComputing #TechHistory #ComputerArchitecture #Innovation #TechMilestones #1990sTech https://dfarq.homeip.net/amd-k6-released-april-2-1997/

¿Algún experto en sistemas operativos o en arquitectura de computadores me puede comprobar que este diagrama es correcto? Lo acabo de crear en @drawio partiendo de varios gráficos de "Sistemas Operativos" de Gary Nutt (Ed. Pearson).

¡Mil gracias!

#OS #computerarchitecture #software #hardware

Diagrama mostrando la interacción entre el sistema operativo y los dispositivos, a través de los controladores de E/S. El proceso de aplicación llama al gestor de dispositivos del sistema operativo, que a su vez tiene drivers (o manejadores), que son los que hablan con los controladores de E/S en el hardware. Estos últimos, a través de sus puertos y de los buses, se comunican con los distintos dispositivos.

Notes on the Pentium's Microcode Circuitry

https://www.righto.com/2025/03/pentium-microcde-rom-circuitry.html

#HackerNews #Pentium #Microcode #Microelectronics #ComputerArchitecture #TechHistory

One of the best interviews on AI and GPUs I've every seen was posted earlier today. Jensen Huang is really super smart in my opinion, and I think this interview is definitely worth watching. I can understand how it was a person like him who turned NVIDIA into a company with a market cap more than 1 trillion USD.

Jensen Huang on GPUs - Computerphile
https://www.youtube.com/watch?v=G6R7UOFx1bw

#NVIDIA #GPU #AI #CUDA #CPU #JensenHuang #ComputerArchitecture

Intel released a new CPU on March 22, 1993. Instead of a part number, it had a brand name. Calling it Pentium instead of 586 helped Intel's problem with clones. https://dfarq.homeip.net/what-came-after-486/ #CPUHistory #ComputerArchitecture #Innovation #TechThrowback #1990sTech #Microprocessors #RetroComputing

Hey everyone involved in #ComputerScience, are you looking for a #job in #academia?

Aalto University in Finland has several positions open for assistant professors. The topics include #MachineLearning, #Programming, #ComputerArchitecture, #CyberSecurity, #SoftwareEngineering and Human-Computer Interactions.

https://www.aalto.fi/en/department-of-computer-science/assistant-professor-positions

The Pentium contains a complicated circuit to multiply by three — https://www.righto.com/2025/03/pentium-multiplier-adder-reverse-engineered.html
#HackerNews #Pentium #Multiplication #Circuit #ReverseEngineering #TechHistory #ComputerArchitecture

If it's not an API, it's an implementation detail.

A nicely-phrased distinction: “On the technical side, I want to stress that there’s no such thing as an undocumented API (or private API). By definition an API is something that’s meant to be called by apps. Things that aren’t APIs are implementation details. And when you use that term it’s easier to evaluate your choices.” — Quinn “The Eskimo!”

Which is all too reminiscent of a common outcome among apps:

"With a sufficient number of users of an API,
it does not matter what you promise in the contract:
all observable behaviors of your system
will be depended on by somebody.” — Hyrum's Law

Platform providers would usually prefer to follow the model “Everything which is not allowed is forbidden" while developers are fond of "Everything which is not forbidden is allowed”.* The former avoids breaking quite as many apps and can deeply annoy, err, limit app developers, while following the latter makes non-breaking platform changes difficult to impossible, and increases support and testing.

At the intersection of those two models is app instability, angst, and architectural limits.

And yes, there are inevitably cases where API designs are just broken, or where the designs reach their architectural limits, and those then either stymy further work, or might get incompatibly un-broken, or preferably get replaced in parallel with better and more capable designs and the older APIs deprecated and removed.

How you design replacements for your API limits is part of your design too, but a part frequently ignored. As are app upgrades.

Limited API designs I've met have included an eight-byte password hash buffer, and APIs featuring 32-bit addressing for storage and memory.

*I'll leave any discussions of Misters Dillon and Cooley for another time.

#computerarchitecture #appdev #compatibility #PlatformEngineering #appdesign

@jfmezei :How long are data blocks for each entry in the in-CPU cache? 64 bits ? 128 bytes ? 1 page ?

It varies. Most implementations will use one cache block size at a time at a given cache level, but that size and the size and the organization of the caches varies.

:Does this vary from architecture to architecture or even inside an architecture?

Yes. Alpha caching varied by processor and by implementation, all within the limits of the Alpha architecture.

:Is it totally transparent when writing at OS level?

Totally transparent? No.

Details, such as what was locally called word tearing, alignment, memory timing, and memory lock processing, all get involved.

Similar requirements can arise in apps.

There are a few other wrinkles I’d prefer to not meet again, too.

Mostly transparent? Yes.

:And in multi core with coherent caches, when a core does a write to RAM, does memory controller propagate this to all other cores in case they have it cached? or does memory controller know which core has what in cache and send only relevant updates?

It depends. Most of what I’ve met will mark the cache contents as being invalid, and will await the next opportunity to wait for main memory to load the data, or to wait for a load from L3, or such. I can’t recall ever working on a cache-coherent multiprocessor that tried to reload the cache everywhere.

Alpha could load cache speculatively, or explicitly, or evict as needed.

http://bitsavers.org/pdf/dec/alpha/system_reference/Alpha_System_Reference_Manual_Version_7_1997.pdf

WP has a reasonable description, as well:

https://en.wikipedia.org/wiki/Cache_(computing)

Deeper still:

https://www.cs.swarthmore.edu/~kwebb/cs31/f18/memhierarchy/caching.html

More for amusement, figures 5 and 6 nicely show the shifting scale of the complexity of modern computer systems:

https://www.computer.org/csdl/journal/ts/2021/06/08704965/19HKUhJMVAQ

#digitalequipment #dec
#alpha #computerarchitecture #retrocomputing

Toward sustainable #computing with an energy-efficient memory innovation: SOT-MRAM #MemoryTechnology could replace cache memory in #ComputerArchitecture in the future 👉 https://press.uni-mainz.de/toward-sustainable-computing-energy-efficient-memory-innovation/
@dfg_public

#SustainableComputing #SOTMRAM #SpinOrbitTorque #OrbitalHallEffect #TopDyn #physics

Energy-efficient memory innovation: SOT-MRAM #MemoryTechnology could replace cache memory in #ComputerArchitecture in the future // #SustainableComputing #SOTMRAM #SpinOrbitTorque #OrbitalHallEffect @NatureComms @ERC_Research @HorizonEU #MainzUniversity
https://nachrichten.idw-online.de/2025/02/06/toward-sustainable-computing-energy-efficient-memory-innovation

Inside SiFive’s P550 Microarchitecture
🔗 https://old.chipsandcheese.com/2025/01/26/inside-sifives-p550-microarchitecture/

"The P550 is a 3-wide out-of-order core with a 13 stage pipeline. Out-of-order execution lets the core move past a stalled instruction to extract instruction level parallelism. It’s critical for achieving high performance because cache and memory latency can be significant limiters for modern CPUs."

#RISCV #RISC_V #ComputerArchitecture #CPU #CPUs #Processor #Processors #Hardware #ComputerHardware #Eswin #EC7700X #SiFive #P550

#ComputerScience Papers Every Developer Should Read in...

#SystemDesign and #Programming Fundamentals
#DistributedSystems
#DataStorage and Processing
System Design and Metrics
Modern Infrastructure
#ComputerArchitecture and Systems Performance

https://newsletter.techworld-with-milan.com/p/computer-science-papers-every-developer

Hmmmmm

#computerarchitecture

RISC-V Vector Extension overview
🔗 http://0x80.pl/notesen/2024-11-09-riscv-vector-extension.html

"The goal of this text is to provide an overview of RISC-V Vector extension (RVV), and compare — when applicable — with widespread SIMD vector instruction sets: SSE, AVX, AVX-512, ARM Neon and SVE.
[…]
The vector extension is quite a huge addition. It adds 302 instructions plus four highly configurable load & store operations."

#RISCV #RISC_V #RVV #ComputerArchitecture #ISA #InstructionSetArchitecture #CPU #CPUs #processor #processors