#eda

Gérald Niel ✅ ☭ Ⓐ 🏴🇵🇸gegeweb@stoneartprod.xyz
2026-02-03

#JazzOBar #EDA #Marcoussis #LosCubanitos

Rico Pilón (Pacho Alonso)

Avec el maestro exceptionnellement au piano !
Notre pianiste attitrée était en déplacement…

Lutz Hühnkenlutzhuehnken
2026-01-29

I came across github.com/confluentinc/parall recently and I think the API makes more sense than the "standard" Kafka client libraries.
It allows parallel processing while keeping per-key ordering, and as a side effect has per-message acknowledgements and automatic retries.
It could use some modernization (recent Java, virtual threads), but conceptually this should be the go-to API for Kafka consumers.
What do you think? Have you used it?

In case you haven't heard it already: we at @fsi have started packaging software, to make awesome #FLOSS available to you #electronics and #chip #designers
Highlight so far include klayout and magic, which are now easily available to you #Guix users through simple invokations, like:

guix shell klayout -- klayout

or

guix shell magic -- magic

#GNU Guix not only allows for most up-to-date packages, #reproducible development and build environments and an absolute dedication to #freesoftware, it also eases contribution, extension and enhancement of already available solutions.

Check it out! Don't hesitate to reach out if you have questions!

f-si.org
guix.gnu.org

#silicon #freesilicon #FOSS #chipdesign #EDA #electronicdesignautomation

AsyncAPI InitiativeAsyncAPISpec@fosstodon.org
2026-01-21

🚀Speaker Reveal!

Join Ignacio Castillejos as he shares a real-world AsyncAPI adoption inside The New York Times Commerce Platform.

From legacy EDA on GCP PubSub to a modern stack using AWS EventBridge, AsyncAPI, and CloudEvents, this session walks through the real technical and organizational challenges behind the transition.

You don't want to miss it!

#AsyncAPIConference #EDA

Lutz Hühnkenlutzhuehnken
2026-01-20

I'll be running a half-day workshop on event-driven architecture in Munich on March 10th. Compact, practical, and I'm told quite enjoyable.
Example code is Java/Kafka/Spring, but concepts apply to any stack. In German 🇩🇪.

- Code "sas_trainer_15_mar2026" for 15% off
- Early-bird (€300 off) ends Thursday, Jan 22nd

➡️ software-architecture-summit.d

mlyoung :blobcatgiggle:mlyoung@tech.lgbt
2026-01-15

New update to Slingshot, my SystemVerilog LSP, has dropped! This is a more minor one: it adds support for completing module instantiations, and importantly fixes a number of deadlocks and race conditions. Upgrading is strongly recommended. enjoy~

github.com/mattyoung101/slings

#foss #eda #systemverilog #lsp

2026-01-11

7/ My advice? Before chasing the latest trend, master the basics.

Learn how to clean data, explore it, and understand it deeply. It’ll take you further than any buzzword ever will.
#Bioinformatics #EDA #DataSkills #KeepItSimple

Max Korbelmaxkorbel
2026-01-08

🌉 ROHD Bridge v0.2.1 released

• Supports new ROHD generation features
• Smarter connectivity analysis (incl. constant tie-offs)
• Improved APIs for complex port structures
• Bug fixes & logging cleanup

ROHD Bridge makes large-scale hardware connectivity fast and programmable—even if you’re not using ROHD.

intel.github.io/rohd-website/

Max Korbelmaxkorbel
2026-01-07

🚀 ROHD v0.6.7 released

• Cleaner generated RTL & SystemVerilog
• Faster simulation for glitchy conditionals
• Improved SSA & write-after-read error messages
• Better debugability and APIs

Learn more: intel.github.io/rohd-website/

Join the discussion: discord.gg/DfD2RuAzzh

2026-01-03

Advent of Code Day 5: Iterates over RAM holding fresh ID ranges. Autopipeline checks N IDs against M ranges each cycle. Easily does N=3,M=2 at ~235MHz, ~1.4 billion ID-in-range checks computed per sec 😎

github.com/JulianKemmerer/Pipe

#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

Advent of Code Day 5: Iterates over RAM holding fresh ID ranges. Autopipeline checks N IDs against M ranges each cycle. Easily does N=3,M=2 at ~235MHz, ~1.4 billion ID-in-range checks computed per sec 😎 github.com/JulianKemmer... #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

github.com/JulianKemmerer...

2026-01-01

Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎

github.com/JulianKemmerer/Pipe

#aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

Advent of Code Day 7: very simple design, good intro to #pipelinec. processing all ~hundreds of elements of an entire line each cycle. ~600 million to ~5.3 billion tachyon beams splitting per second. 😎 github.com/JulianKemmer... #aoc25 #fpga #hardware #verilog #vhdl #hdl #rtl #hls #asic #eda

github.com/JulianKemmerer...

Lutz Hühnkenlutzhuehnken
2025-12-30

🎉 500 ⭐️ on Awesome Event-Driven Architecture!

Thanks to everyone who starred, shared or contributed. It’s great to see the EDA community at work and exchanging patterns, tools, and real-world lessons.

If you’re interested in event-driven microservices and architectural patterns, have a look:
➡️ github.com/lutzh/awesome-event

Image of the star counter on Github showing 500.
Dariusz Gafkadgafka@phpc.social
2025-12-26

To implement an Event-Driven Architecture, we end up following either the "Smart Endpoints, Dumb Pipes" approach or the "Dumb Endpoints, Smart Pipes" approach — either consciously or not.

In my latest article we will dive into those approaches to find out what do they actually mean, and which one will help keep the system simple as it grows.

blog.ecotone.tech/implementing

#php #eda #programming #messaging #events

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