#osvvm

2025-10-10

@guix Other than as package manager on top of #archlinux, I’m using #guix for electronics design, mostly #vhdl and #fpga related stuff.

I run simulations with help of #hdlmake using #ghdl compiler, #osvvm for verification, #cocotb for testbenches, #yosys for synthesis, #nextpnr for placement and routing and #openFPGALoader for flashing. Finally, I use my own Guix channel to package gateware and run #ci tests on #sourcehut Guix image. A demo toy example of this runs here

builds.sr.ht/~csantosb/job/158

2025-06-01

Uses verification #osvvm library and #openlogic standard #vhdl, along with #ghdl for simulation, #hdlmake for project creation and #yosys for synthesis.

All dependencies are manipulated with a declarative manifest file.

git.sr.ht/~csantosb/ip.alu/tre

2024-11-05

#ci testing of a #vhdl project in the #sourcehut build farm.

It runs a #ghdl simulation using the #osvvm verification library, creating a #guix local profile from a manifest file to handle all dependencies. Requirements are pulled from a custom repository. All #reproductible thanks to pinned guix channels.

builds.sr.ht/~csantosb/job/136

#modernhw

2024-06-19

Well after 14 years I'm laid off from Viavi. This has been a particular nightmare for me for 14 years since I was a victim of the 2008 financial meltdown and laid off then and couldn't find work for all of 2009. It was rough.

But anyway, locally fantastic staff and great people to work with. Higher management, no comment as I am negatively biased. We made some cool stuff and I will miss seeing how my current baby will turn out.

Anyhow I don't really know how far this might go, but if someone is looking for a #EE with 25 years experience in digital design primarily with #FPGA and #VHDL (and a smattering of #Verilog), including verification mainly using #OSVVM and #UVVM (the latter modeled after #UVM) please contact me, especially if you can support remote work. I do have a professional office at home, it can be YOURS (along with me of course).

(And if so inclined, boosting this for greater visibility in networks is greatly appreciated.)

#OSVVM looks pretty nice, modulo the naming convention which is kinda cringe, unlike #UVM it does really contain actual helpful utilities, not just a standardised interface

#FPGA #ASIC #VHDL #SystemVerilog #Verilog
2023-07-31

Our amazing IT department is finally getting around to a ticket I submitted in April regarding unfucking their security software and a #VHDL language server (github.com/VHDL-LS/rust_hdl). So I tinkered with the newest version of it this morning and it seems to still have the same errors as before. Seems to completely fail to pick up certain files and then also doesn't support genericized packages, based on how it's throwing a fit over #OSVVM. Might have to see if I can get #GHDL working on Windows without too much annoyance.

Don't have too much hope though. On the plus side I don't NEED it. It'd just be a nice to have capability and I'd like to experiment with Emacs #eglot with my language of choice.

2022-12-01

What open source #VHDL framework should I use ?
#OSVVM or #UVVM ?

Maybe I should just keep #Cocotb ;)

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