@thezoq2 Begin page 392 in pdf.

#fpga #surfer #verilog #vhdl #spinalHDL #chisel #icarus #verilator #simulation #opensource #gtkwave #waveform

#80C52 softcore + 12kB on-chip ROM + on-chip 16kB RAM implemented on Altera #CYCLONE IV #EP4CE6 running with BASIC-52+I2C at 11.0592MHz
controlling #RDA5807 FM tuner through I2C bus.
We can directly enter channel frequency and volume or using SEEK mode for UP or DOWN scan.
#vhdl #mcs8051 #softcore #intel #verilog

Programming ATF1508 CPLDs using Altera Quartus II, a bunch of other tools and the Adafruit FT232H Breakout

https://www.steckschwein.de/post/2025/07/cpld-upgrade-new-toolchain/

#vhdl #cpld #atf1508 #altera #openocd #retrocomputing

I looked... and it appears there are no STEELMAN-like requirements that preceded #VHDL.

what I read is that the language was developed in cooperation with IEEE and other industry players.

this makes me think there were developing requirements that were never published.

Suspiciuously cheap ATF1508 from eBay have arrived. And they indeed _are_ ATF1508, and they work (at least the one I tried does).

Who would have thought?

#vhdl #retrocomputing #cpld #pld #electronics

CADR4 #MIT #CADR #LispM #LispMachine current status is we are optimizing the simulation runtime (it takes about 10 minutes to run through almost all the boot PROM to the point we are accessing memory -- which isn't fun when you want to work on accessing memory).

#Lisp #VHDL #HDL

https://github.com/ams/cadr4

On to new adventures!

#retrocomputing #cpld #atf1508 #vhdl #6502microprocessor

iceprog blinky.bin
init..
cdone: high
reset..
cdone: low
flash ID: 0x20 0xBA 0x16 0x10 0x00 0x00 0x23 0x80 0x80 0x52 0x17 0x00 0x92 0x00 0x30 0x09 0x05 0x18 0xBC 0xBD
file size: 32220
erase 64kB sector at 0x000000..
programming..
done.
reading..
VERIFY OK
cdone: high
Bye.

#Opensource #fpga #vhdl #verilog

the first example was to old, the #yosys Software changed the last years. But now I get an example to work. Nearly everything worked out of the box. After adding a udev/rules.d even programming worked!!! #Yeah

#Opensource #fpga #vhdl #verilog

@jalefkowit

It's an interesting point you highlight because I've never thought of things through that paradigm. Now that I see it, I realise I'm hoping to transition to #openBSD because I believe of mainstream operating systems, it probably has the best #DX.

In this particular case, I believe that the developers exploit that in order to optimise for what might be called #security which impresses me.

I realise it's probably an outlier in this regard!

#developerExperience #cybersecurity #quality #systemArchitecture #cybernetics #complexSystemsTheory #qualityAssurance #Deming #Shuart #design #software #coding #softwareEngineering #abstraction #electricalEngineering #HDL #VHDL #theresNoSuchThingAsSoftware

В русских клубах Америки можно делать не только дискотеки и выступления писателей, но и митапы по FPGA

В городах Америки и Канады, где живут много наших соотечественников, существуют русские клубы, в которые ходят на дискотеки и викторины, для игру в мафию и на выступления писателей. В столице Калифорнии городе Сакраменто, где живет около 80 тысяч русских и украинцев, а также есть армянский и молдавский рестораны, таким клубом является Synergy Social Club. В этом клубе я недавно провел просветительский митап по главной технологии современной цифровой микроэлектроники: маршруту проектирования RTL-to-GDSII для микросхем в массовых изделиях типа смартфонов, и связанной с этим маршрутом технологии FPGA, которые применяются для прототипирования ASIC-ов и обучения в университетах будущих проектировщиков. Эти технологии полезны в наше тревожное время для надежного трудоустройства в самых разных местах: от производителя ракет Lockheed Martin до производителя айфонов Apple. Вот примеры объявлений:

https://habr.com/ru/articles/919640/

#Verilog #VHDL #FPGA #ASIC #Gowin #сакраменто #Open_Sauce #SystemVerilog #Veriog_Meetup #школа_синтеза_цифровых_схем

Two hackers going at it ... https://github.com/ams/cadr4/commits/master/ #LispM #LispMachine #MIT #CADR #FPGA #VHDL

LFSR CPU Running Forth

https://github.com/howerj/lfsr-vhdl

#HackerNews #LFSR #CPU #Forth #VHDL #HackerNews

Uses verification #osvvm library and #openlogic standard #vhdl, along with #ghdl for simulation, #hdlmake for project creation and #yosys for synthesis.

All dependencies are manipulated with a declarative manifest file.

https://git.sr.ht/~csantosb/ip.alu/tree/test/item/.builds/manifest.scm

Simple ALU toy #digitalelectronics design in #vhdl, with a demo of a full #ci pipeline using #sourcehut build capabilities, coupled to #guix for dependency handling.

https://git.sr.ht/~csantosb/ip.alu/tree/test/item/README.md

#Guix channel for #digitalelectronics design, mainly #vhdl and #fpga.

The list of available packages

https://git.sr.ht/~csantosb/guix.channel-electronics/tree/main/item/packages.md

Includes -next and -latest versions of #guix tagged packages, as well as #gateware code: fw-open-logic, fw-en_cl_fix, osvvm, etc.

Get it

git clone --depth=1 https://git.sr.ht/~csantosb/guix.channel-electronics

Install with:

guix install -L ./guix.channel-electronics PACKAGE

#modernhw

MEGA65 Audio Amp Fix: Solving the R3 Internal Speaker Issue
#MEGA65 #AudioAmplifier #TechFix #RetroComputing #VHDL #Troubleshooting #InternalSpeakers #SSM2518Amp
https://theoasisbbs.com/mega65-audio-amp-fix-solving-the-r3-internal-speaker-issue/?feed_id=3448&_unique_id=683072ff12743

The search engines are failing me.

Dear Lazy Web:
If I wanted to enumerate the hierarchy of a design at the beginning of a cocotb test bench, how would I do it? (I'm aware of _discover_all(), but can't figure out how to iterate the results to print them.)

Extra credit: How do I get an interactive debugger to break within the cocotb python code if I call cocotb from pytest? It seems to run the pytest code in the debugger, but not the cocotb code.

#fpga #cocotb #lazyweb #python #vhdl #verilog

GNU/ #emacs as a full fledged #vhdl #ide, using #guix.

https://git.sr.ht/~csantosb/emacs.vhdl-ide

Ersatz für das Gate-Array in der 1541

Es gibt nur wenige Komponenten im Commodore 1541-Laufwerk, die gerne sterben. Das Gate Array, UC1 oder MOS 325572-01 ist eines davon. Und Ersatz ist nicht billig. Aber man kann sich auch einfach selber eines bauen.

#1541 #32557201 #Array #commodore #CSG #EasyGate1541 #FPGA #Gate #MOS #PCB #PLA #Replacement #Schematic #VC1541 #VHDL #XC95144XL #XC9572XL

https://dirkwouters.de/easygate1541/