Lmst

#FPGA dorks. I'm running into an issue where #vivado says: multiple drivers on MMCM pins when I use a known good block (LVDS deserializer from appnote xapp523) in the vivado block diagram for a 7 series #xilinx #zynq part (snickerdoodle black). I get the error even if I pin out directly to top level pins. I hate using the gui because it hides too much magic. Has anyone hit this madness before?

I'm trying to deserialize a 1.024 Mbps 8b10b lvds to get it on the linux side for storage on disk.

FPGAspreading way of synthesis.

- Download `tar`archive : 125GB
- Unflat archive : +125GB
- Launch installer and install : + 210GB

Total space required for full installation : 460GB !

#fpgastreading #fpga #xilinx #vivado #amd

A photo of a man's legs sitting in the Stockolm metro. The legs are spread and the woman sitting next to him is forced to squeeze her legs by pushing herself.

The top of the man's legs are hidden by the image of a BGA-type electronic component with Xilinx printed on it.

Image source from wikipedia : https://fr.wikipedia.org/wiki/Manspreading

Hmm qu'est-ce que je supprime pour faire de la place ?

#quartus #altera #xilinx #vivado

Un camemberg représentant graphiquement l'utilisation du disque dur avec 774.5GiB d'occupation.
Les deux moitier principales sont représentées par le dossier Quartus et Xilinx.

Затолкаем братцы!!! UART Lite через PCIe прямиком в Linux: драйвер за вечер (почти)

Что если можно было бы подключить своё AXI-устройство на FPGA к Linux через PCIe за вечер? В этой статье рассказываю, как написать драйвер для UARTLite через XDMA, собрать свою TTY и начать работать с GPS прямо из терминала! Залетай, что смотришь....

https://habr.com/ru/articles/900644/

#fpga #linux #linux_kernel #uart #pcie #tty #axi #vivado #embedded #driver

Затолкаем братцы!!! UART Lite через PCIe прямиком в Linux: драйвер за вечер (почти)

Что если можно было бы подключить своё AXI-устройство на FPGA к Linux через PCIe за вечер? В этой статье рассказываю, как написать драйвер для UARTLite через XDMA, собрать свою TTY и начать работать с GPS прямо из терминала! Залетай, что смотришь....

https://habr.com/ru/articles/900644/

#fpga #linux #linux_kernel #uart #pcie #tty #axi #vivado #embedded #driver

Not having #AMD #Xilinx #Vivado #Chipscope based live #hardware debug for the #picoice #Lattice #ice40 #FPGA was a little annoying

so I am hoping to revive the small pipelinec project that was sorta a build your own chipscope attempt 🤙 and demo that on the pico ice

LEDを1Hzで点滅させる回路を作成する
https://qiita.com/GeekMasahiro/items/45c4312c24069641f9c3?utm_campaign=popular_items&utm_medium=feed&utm_source=popular_items

#qiita #Verilog #FPGA #Vivado #EBAZ4205

@PypeBros #Vivado does this. You can zoom in on an image of the device and see exactly which signals have been placed where, which bits of logic are in which LUTs etc.

I am currently writing a Python script to generate a TCL file that can sourced by another TCL script and run inside Vivado to modify a netlist.

What am I doing….

#FPGA
#Vivado
#Python
#TCL

#AMD #Vivado Design Suite Essentials

https://www.adiuvoengineering.com/amd-vivado-design-suite-essentials

The #Vitis Unified Software Platform enables developers to more easily tap into the benefits of #Xilinx heterogeneous #SoCs and accelerate their applications.

Is there a way in Vivado to make it dark, not just the text editing window, the whole thing?
Or even all the windows (like sources, design runs, output, etc) at a push ?

It's such a major missing feature.

#FPGA #XILINIX #VIVADO

so far there's just one thing that drives me mad about #VHDL, or maybe specifically it's implementation in #Vivado:
if I name a component not exactly as the entity and forget to add corresponding configuration, it simply won't create the instance in the architecture and won't connect the signal, and issue no error whatsoever, just silently continue as if nothing happened
and then if I add the configuration, it still refuses to pick it up and doesn't create the instance :blobcatangry:
this ought to be a bug, should try it on #GHDL perhaps

in other respects it's pretty nice to write in, at first there are more, sometimes silly, errors (like you have gazillion of types which all are essentially a bit vector¹, and the type-checker will fuck with you if you aren't properly converting one into the other), and there are much fewer syntactic constructs than in #Verilog, let alone #SystemVerilog, that you're forced to wrap it all properly, but then, if it works, it works correctly, the way you intended
I pretty much want to try and use #Ada for a firmware, and I don't care if the tool-chain is proprietary (is #GNAT proprietary?) — the FLOSS enthusiasts should adopt better standards if they want me to use their stuff and contribute more

¹ boolean, bit, std_logic for single bit; arrays thereof; std_logic_vector, signed, unsigned, integer, natural, positive, time, and real are all mutually incompatible, modulo few exceptions
if-then-else only works with booleans, you can't just put a value of std_logic in place of the condition

today I've apparently found a bug in #Vivado — due to a combination of an interface with inout ports, driven from a class within the interface, which then gets overloaded by reassigning type value in a static property of another class (factory), the interface itself gets passed to module, then the values of a signal sampled on posedge within the module and outside of it became different and broke (AXI) handshaking
guess AMD should hire me already

the model I used was total shit just waiting to stab me in the back, I just couldn't find anything better and wanted to avoid implementing even AXI Lite by myself, then I searched again and found #TVIP #AXI which seems pretty solid so far

https://github.com/taichi-ishitani/tvip-axi

#Verilog #SystemVerilog

On the positive side, the files reported unreadable were all various things under /work/xilinx/Vivado/2019.2/...

So, if I'm lucky I haven't lost anything important and Vivado has finally proved itself useful... as a 25GB ablative shield for the rest of my project data on that volume...

#backups #vivado #surprise

Linux From Scratch на Zynq UltraScale+ MPSoC

В данной статье я постараюсь описать процесс создания кастомного образа Linux на Zynq UltraScale+ MPSoCс. Каждый необходимый компонент будет собран отдельно с использованием соответствующих утилит. Статья разбита на разделы, которые шаг за шагом знакомят вас с процессом сборки и запуска системы на данной платформе.

https://habr.com/ru/articles/805171/

#zynq #zynqmp #linux #vivado #vitis

Wow, newer #Vivado version just grab focus whenever they want. Why do you hate your users/devs, Xilinx? -.-

Searching for #Vivado related issues on #Google, I found that #Reddit and #Xilinx Forum threads are on par in terms of not-helping-out-ness.

Wrote up a bunch of automation scripts to set up a #Vivado AMS instance and automated build of cores. Due to the genius of @enjoy_digital #LiTeX tech, all working cores were built for a different FPGA (K325T 3x MiSTer) in a day (5h build time, $5 AWS).

https://youtu.be/hXLaA0ITzy8

It is currently not possible to import a Block Design into a Non-Project flow in Vivado. Block Designs are the foundational construct of IP Integrator-based designs.

The Block Design configuration can be exported as a TCL script which can then be sourced in a build script for Project Scripted flow, making the repository storage overhead very low.

#FPGA
#AMD
#Vivado

So. Geht. Das.

#vivado #pynqz1 #flash #qspi

#vivado

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