What is impressive here is the availability of this feature in #JuliaLang #JuliaPackaging - when compared with competing programming environments:

* #dotnet #NuGet only has crude runtimes like #x64, and #arm64.

* #python #PyPI wheels seems equally constrained with #manylinux supporting plain, e.g., #x86_64, and #aarch64.

Not to mention #BinaryBuilder in general with support for e.g. #musl, #armv7l, #bsd and #riscv64

Whatever the number of applications of #microarchitecture specific binaries.

SciTech Chronicles. . . . . . . . .April 17th, 2025

https://bit.ly/stc041725

#Donaldjohanson #SwRI #"12.5 light minutes away" #"observation sequence" #raindrops #"plug flow" #10% #"electrically conductive polymer" #"Neurospora crassa" #"Sporosarcina pasteurii" #mineralized #microarchitecture #Hyperadaptor #nickel-based #temperature-insensitive #"sudden or extreme temperature changes" #"high-bed cultivation" #Lidar #disease #pruning

📈 Ah, the old "Calculate Throughput with LLVM's Scheduling Model" routine—because nothing screams weekend fun like diving into compiler internals and #microarchitecture performance analysis! 🤓 Just remember, when life gives you throughput, measure it in #IPC and don't forget to bring your inverse throughput for extra giggles. 😂
https://myhsu.xyz/llvm-sched-interval-throughput/ #CalculateThroughput #LLVM #SchedulingModel #CompilerInternals #PerformanceAnalysis #HackerNews #ngated

example: ordering of memory writes.
on a strongly ordered system, writes are reordered to program order before commiting (actually writing to D$). On a weakly ordered memory system, writes to different locations can happen in different order #uarch #comparch #microarchitecture

Last week, @lavados and his PhD students went to Germany and visited #µASC and #RuhrSec!

PhD candidate @notimaginary_ presented his paper “An Analysis of HMB-based SSD #Rowhammer”. 📑👇
https://uasc.cc/proceedings25/uasc25-juffinger.pdf

#Microarchitecture #security #informationsecurity #cybersecurity #conference

Wikichip is back ? Wikichip is BACK 🥳

(And I've archived the tables of CPUID immediately, just in case).

#uarch #microarchitecture #cpu

Flow Computing aims to boost CPUs with ‘parallel processing units’
https://spectrum.ieee.org/parallel-processing-unit
#ycombinator #computer_architecture #cpu #microarchitecture #parallel_processing

100x Faster CPUs from Finland's New Startup
https://spectrum.ieee.org/parallel-processing-unit
#ycombinator #computer_architecture #cpu #microarchitecture #parallel_processing

One #Prime Day this is probably a good time for me #SRE #DevOps #Reliability #Microarchitecture top tip:

Avoid powers of ten: use prime numbers as your magic constants.

All the beginners use powers of ten: “we can accept 10 connections!” “I have a 10 second timeout!” “Limit to 100 seconds of CPU!”

Congrats you read the Baby Tutorial.

Ready to grow up? Analyse the data then pick the nearest prime:

11 connections
19 second timeout
97 seconds of CPU

It makes it way easier to diagnose issues.

Turns out @cheese is a real 3D person!

Here he sits down with Mike Clark, chief architect of Zen, to talk about AMDs latest microarchitecture, #zen5

#HPC #x86 #microarchitecture #avx512

From: @chipsandcheese
https://techhub.social/@chipsandcheese/112790635587132915

"Intel’s Lion Cove Architecture Preview" #MicroArchitecture #LionCove #Intel

https://chipsandcheese.com/2024/06/03/intels-lion-cove-architecture-preview/

https://thechipletter.substack.com/p/ai-accelerators-the-cambrian-explosion

#riscv #ai #microarchitecture

AMD Zen 5 Execution Engine Leaked, Features True 512-bit FPU

Giving "Zen 5" a 512-bit FPU meant that AMD also had to scale up the ancillaries [..]. The L1 Data cache has been doubled in bandwidth, and increased in size by 50%. The L1D is now 48 KB in size [..]. FPU MADD latency has been reduced by 1 cycle. Besides the FPU, AMD also increased the number of Integer execution pipes to 10, from 8 on "Zen 4."

https://www.techpowerup.com/321201/amd-zen-5-execution-engine-leaked-features-true-512-bit-fpu

#AMD #Zen5 #CPU #FPU #AVX512 #Microarchitecture

The Complete #History of the Home Microprocessor:

https://www.youtube.com/watch?v=EJh4BIujpHA

#Tech #CPU #Microarchitecture #x86 #Processor #ARM #PowerPC #68k

#Zen4c: #AMD’s Response to #Hyperscale ARM & Intel Atom
#Bergamo, AMD’s upcoming 128-core server part sets new heights in #x86 #CPU performance. At the heart of Bergamo is #Zen 4c, a brand-new CPU core variant of their successful #5nm #Zen4 #microarchitecture that enables the push toward more cores per socket. Zen 4c enables Bergamo to fit 1.33x the number of cores in the same #SP5 socket and 360W TDP, with identical L1 and 1MB L2 private caches to Zen 4.
https://www.semianalysis.com/p/zen-4c-amds-response-to-hyperscale

Referenced link: https://www.computer.org/volunteering/awards/rau
Discuss on https://discu.eu/q/https://www.computer.org/volunteering/awards/rau

Originally posted by IEEE ComputerSociety / @ComputerSociety: http://nitter.platypush.tech/ComputerSociety/status/1659287515306553349#m

The #IEEECS B. Ramakrishna Rau award honors those who have made substantial contributions in the field of #computer #microarchitecture and compiler code generation. Celebrate a colleague and submit a nomination for the award before June 1st @ https://www.computer.org/volunteering/awards/rau

#IEEE

Referenced link: https://www.computer.org/volunteering/awards/rau
Discuss on https://discu.eu/q/https://www.computer.org/volunteering/awards/rau

Originally posted by IEEE ComputerSociety / @ComputerSociety: http://nitter.platypush.tech/ComputerSociety/status/1654210308926324738#m

The #IEEECS B. Ramakrishna Rau award honors those who have made substantial contributions in the field of #computer #microarchitecture and compiler code generation. Celebrate a colleague and submit a nomination for the award before June 1st @ https://www.computer.org/volunteering/awards/rau

#IEEE