https://builds.sr.ht/~csantosb/job/1500903#task-compile_osvvm
custom #makefile testing
https://builds.sr.ht/~csantosb/job/1500903#task-test
#hdlmake simulation
https://builds.sr.ht/~csantosb/job/1500903#task-test_hdlmake_sim
and #yosys synthesis
https://builds.sr.ht/~csantosb/job/1500903#task-test_hdlmake_synth
Uses verification #osvvm library and #openlogic standard #vhdl, along with #ghdl for simulation, #hdlmake for project creation and #yosys for synthesis.
All dependencies are manipulated with a declarative manifest file.
https://git.sr.ht/~csantosb/ip.alu/tree/test/item/.builds/manifest.scm
Jay GateMateA1-EVB by Olimex arrived today. Too bad I have to do "grown up" things tomorrow.
@adanskana
#ghdl, in its 5.0.1 llvm variant, is hosted in the electronics channel, and waiting to be merged in #guixscience channel (which provides guix substitutes), where it belongs, see
https://codeberg.org/guix-science/guix-science/pulls/87
The reason for not being part of #guix itself is its dependency on #gnat ada compiler, which cannot be bootstraped at this point. Remember we also have ghdl #lsp and the ghdl #yosys plugin.
The channel aggregator is here, by the way: https://toys.whereis.social/
Jeux de la vie sur fpga \o/
https://video.ploud.fr/w/ryoWzx42nJjaAsk3Rb2H8t
#gatemate #gatemateA1_evb #gameoflife #fpga #flf #yosys #openFPGALoader
Армения посреди Америки, Китая и России: отчет с EDA Connect 2025
Мысль, что Армения удобна тем, что соединяется и с Америкой, и с Китаем - высказал мне один из китайских участников конференции EDA Connect . А мысль, что Армения соединяется еще и с Россией - возникала естественно при просмотре докладов о логическом синтезаторе, статическом анализаторе и верификации с помощью UVM. Помимо докладов, при конференции прошел хакатон по Verilog и FPGA , на который пришли студенты из Ереванского университета, русско-армянского университета, американо-армянского, французско-армянского, европейско-армянского, и других университетов. Занятно, что второй день хакатона проходил в комнате напротив зала, где большое начальство встречалось с Премьер-Министром Армении. Один из студентов хакатона перепутал дверь, и его перенаправила секьюрити.
https://habr.com/ru/articles/891814/
#Армения #Synopsys #Mentor_Graphics #Verilog #SystemVerilog #Gowin #FPGA #Yosys #Utopia #UVM
We had a very productive #FSD meeting earlier today! Check out what we accomplished: https://www.fsf.org/blogs/licensing/fsd-meeting-recap-2025-02-21 #FreeSoftware #Licensing #nextpnr #Yosys
I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.
"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."
https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/
#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5
Just got a 32-bit RISC-V SoC programmed into the Lattice ECP5 FPGA on Radiona's ULX3S using the completely open source LiteX toolchain, including yosys and nextpnr.
#fosh #foss #oshw #fpga #riscv #linux #litex #yosys #nextpnr
quick question about #verilog, or maybe more specifically #yosys: i've been messing around with an icebreaker fpga recently, and the ice40up5k chip has four banks of 32k x 8 bit spram built in. i wanted to use this ram in a design, but (either yosys or nextpnr, i'm not sure which is responsible for assigning hdl declarations to actual hardware) won't automatically assign things to this spram, so you have to manually work with it by instantiating a module of type `sb_spram256ka`. my question, then, is why yosys doesn't mind me using here a module that i haven't defined. since i've told it that i'm using an ice40 chip, is it just implicitly defining a bunch of modules?
The person who is porting #Yosys #NextPrN to #Gatemate on the #olimex board, is discussing his work on this Discord channel. #fpga #digitalmath #addition #multiplication #gaussianlogarithms.
guix crash course
Just purchased some new FPGA toys... An iCESugar and a pico-ice.
I'd like to finally play around with yosys and nextpnr. Looks like yosys is a bit old on Void, and there isn't a nextpnr package.
I'm half tempted to go through the effort of packaging these for Void Linux so others can benefit.
#FPGA #yosys #icesugar #pico_ice
Адаптация платы Colorlight 5A-75B для примеров «Школы синтеза цифровых схем»
Привет! Начался новый поток «Школы синтеза цифровых схем» и я хотел бы поделиться своим опытом по адаптации бюджетной платы с ПЛИС для запуска на ней лабораторных работ Школы. Отдельным преимуществом такого решения является возможность использования Open Source маршрута для синтеза и моделирования цифровых схем на базе Yosys и Icarus Verilog. Colorlight 5A-75B не является отладочной платой в привычном понимании этого понятия - будет интересно.
https://habr.com/ru/articles/849592/
#плис #fpga #yosys #lattice #verilog #systemverilog #icarus #gtkwave
With #guix, this is what it takes to produce a netlist for the 7 series of #xilinx #fpga devices.
> guix install yosys-clang ghdl-clang ghdl-yosys-plugin
> yosys -p 'ghdl --std=08 leds; synth_xilinx -top leds -family xc7 -ise'
It uses only #freesoftware, with #yosys and the #ghdl synthesis module as its backend.
