Gee!
ADC went through #yosys and #nextpnr!

Does it work on hardware? Absolutely not!🤣
#apicula#fpga#gowin#sipeed

This is a wiki about processing video in real time using microcontrollers, ASICs and FPGAs. The related paper was accepted for the Open Source Hardware Conference in Chemnitz Germany, Nov 24-25 2025.

Comment on the page by replying to this toot. #Introduction

#OSHOP #OpenSource #Hardware #FPGA #Yosys #Nextpnr #Video #Pipelines #Introduction

https://wiki.pythonlinks.info/video

Fully #freesoftware based support for GateMate FPGAs from Cologne Chip [0] just landed in #guix.

It includes #yosys for synthesis, #openFPGALoader for device flashing and #nextpnr for placement and routing.

guix shell -C -m manifest.scm -- make

The whole toolchain runs in a #sourcehut #ci pipeline.

https://builds.sr.ht/~csantosb/job/1588460#task-test

[0] https://indico.cern.ch/event/1587509 for details on #gatemate #fpga.

@guix Other than as package manager on top of #archlinux, I’m using #guix for electronics design, mostly #vhdl and #fpga related stuff.

I run simulations with help of #hdlmake using #ghdl compiler, #osvvm for verification, #cocotb for testbenches, #yosys for synthesis, #nextpnr for placement and routing and #openFPGALoader for flashing. Finally, I use my own Guix channel to package gateware and run #ci tests on #sourcehut Guix image. A demo toy example of this runs here

https://builds.sr.ht/~csantosb/job/1585413

One step closer to UNIX v1 using open source toolchain: https://github.com/YosysHQ/yosys/pull/5411

#pipdp11 #yosys #gowin #fpga #retrocomputing

News about GW5 series - PLL went through #yosys, #nextpnr, and #apicula and started working!🍾

At the moment, there are a huge number of crutches, which I plan to remove in the near future and make the appropriate PR.😉 #fpga#gowin#sipeed

@PaulaMaddox Well, I've got the gui tool installed and I see I can start with a demo that echoes data back via the Ft+ V2... that seems like a great start.

Crossing fingers.

I'm not worried about an upload tool much. More about design lock in or other anti-patterns.

I'd love to get experience with #yosys and #nextpnr and maybe this will be my excuse to try.

the first example was to old, the #yosys Software changed the last years. But now I get an example to work. Nearly everything worked out of the box. After adding a udev/rules.d even programming worked!!! #Yeah

#Opensource #fpga #vhdl #verilog

#ci logs with #osvvm builds

https://builds.sr.ht/~csantosb/job/1500903#task-compile_osvvm

custom #makefile testing

https://builds.sr.ht/~csantosb/job/1500903#task-test

#hdlmake simulation

https://builds.sr.ht/~csantosb/job/1500903#task-test_hdlmake_sim

and #yosys synthesis

https://builds.sr.ht/~csantosb/job/1500903#task-test_hdlmake_synth

Uses verification #osvvm library and #openlogic standard #vhdl, along with #ghdl for simulation, #hdlmake for project creation and #yosys for synthesis.

All dependencies are manipulated with a declarative manifest file.

https://git.sr.ht/~csantosb/ip.alu/tree/test/item/.builds/manifest.scm

Jay GateMateA1-EVB by Olimex arrived today. Too bad I have to do "grown up" things tomorrow.

#fpga #opensource #yosys #olimex

@adanskana
#ghdl, in its 5.0.1 llvm variant, is hosted in the electronics channel, and waiting to be merged in #guixscience channel (which provides guix substitutes), where it belongs, see

https://codeberg.org/guix-science/guix-science/pulls/87

The reason for not being part of #guix itself is its dependency on #gnat ada compiler, which cannot be bootstraped at this point. Remember we also have ghdl #lsp and the ghdl #yosys plugin.

The channel aggregator is here, by the way: https://toys.whereis.social/

Jeux de la vie sur fpga \o/

https://video.ploud.fr/w/ryoWzx42nJjaAsk3Rb2H8t

#gatemate #gatemateA1_evb #gameoflife #fpga #flf #yosys #openFPGALoader

Армения посреди Америки, Китая и России: отчет с EDA Connect 2025

Мысль, что Армения удобна тем, что соединяется и с Америкой, и с Китаем - высказал мне один из китайских участников конференции EDA Connect . А мысль, что Армения соединяется еще и с Россией - возникала естественно при просмотре докладов о логическом синтезаторе, статическом анализаторе и верификации с помощью UVM. Помимо докладов, при конференции прошел хакатон по Verilog и FPGA , на который пришли студенты из Ереванского университета, русско-армянского университета, американо-армянского, французско-армянского, европейско-армянского, и других университетов. Занятно, что второй день хакатона проходил в комнате напротив зала, где большое начальство встречалось с Премьер-Министром Армении. Один из студентов хакатона перепутал дверь, и его перенаправила секьюрити.

https://habr.com/ru/articles/891814/

#Армения #Synopsys #Mentor_Graphics #Verilog #SystemVerilog #Gowin #FPGA #Yosys #Utopia #UVM

Again, almost all the credit should go to @acqrel, she is the one who built the #yosys backend for this thing, I just took my existing core, removed all but 4 registers and programmed it

We had a very productive #FSD meeting earlier today! Check out what we accomplished: https://www.fsf.org/blogs/licensing/fsd-meeting-recap-2025-02-21 #FreeSoftware #Licensing #nextpnr #Yosys

\o/

Vive l'opensource,
vive le FPGA libre
vive l'europe ;)

🇪🇺

https://blog.yosyshq.com/p/an-open-source-fpga-toolchain-for-a-large-european-space-grade-fpga/

#yosys #europe #fpga #flf #nextpnr

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

@acqrel's #yosys backend for this thing works 👀🎉

Just got a 32-bit RISC-V SoC programmed into the Lattice ECP5 FPGA on Radiona's ULX3S using the completely open source LiteX toolchain, including yosys and nextpnr.

#fosh #foss #oshw #fpga #riscv #linux #litex #yosys #nextpnr