If someone wants to help me debug my Lattice ECP5 SSPI programming issue: I uploaded the pulseview (logic analyzer) dumps of the SPI link: https://limewire.com/d/8Xdrk#iWBdBVyut2

You can open this with pulseview and add a SPI decoder.

#fpga #ecp5 #opensource #SucreLA

Do you know some source code out there that programs a Lattice ECP5 FPGA via SSPI interface? (and not jtag nor spi flash nor parallel itf)

I am trying to implement it and so far I think I'm really close but something does not work yet... 🤔

PS: I've read countless times the sysCONFIG manual 😭

#ecp5 #lattice #fpga #opensource

Pro tips when using Migen's SyncFIFO() module in your pipeline design...

I went from 70 MHz max frequency to 100+ MHz by just adding this parameter: `buffered=True`

It helped a lot for timing closure of the design :)

#FPGA #ECP5 #OpenSource #LiteX #Migen #SucréLA #HydraSucréLA

I started a project page to document my first FPGA project on a long while, mainly so that I don't forget, but could possibly be useful to others... I'll plan to add subsequent projects and make more progress on this one in the next few weeks and months.

"I bought myself a Radiona ULX3S from CrowdSupply, which includes the 85k Lattice ECP5 FPGA, which can be programmed to simulate the open source 32-bit RISC-V CPU with a completely open source LiteX-yosys-nextpnr, toolchain."

https://blog.bomorgan.io/hobbies/hardware/fpgas/litex-riscv-ecp5-ulx3s/

#riscv #foss #fpga #litex #yosys #nextpnr #linux #crowdsupply #radiona #ulx3s #lattice #ecp5

https://www.reddit.com/r/FPGA/comments/1hvtgn9/fpga_developers_forum_2025_call_for_abstracts/

#fpga #conference #cfp #gatemate #ice40 #ecp5 #xilinx #altera #lattice

The 50€ #olimex #Gatemate board is a great value.

https://www.olimex.com/Products/FPGA/GateMate/

The extension boards make it a very viable choice.

https://github.com/intergalaktik/Extension_Boards_for_Olimex_GateMate
@olimex #fpga #ECP5 #pico-ice

Routing in progress!

#ECP5 #HydraUSB3 #SucreLA

@BrunoLevy01 I have several #FPGA boards here. Three of them have an #ICE40 FPGA, three of them are Xilinx-based, and the last is the #ECP5 evaluation board with an ECP5-5G 85F. Which do you recommend for your FPGA tutorial series? Thank you!

Clearly the #LatticeSemi #ECP5 (and iCE40) #FPGA dominates the landscape of #yosys / #nextpnr compatible dev kits but where are the #Nexus board? Anyone knows why? Availability, unfamiliarity, value, performance?

AHHHH! I finally got a ring oscillator working on #ECP5 with the #Yosys / #Nextpnr tool chain (I’m not complaining, I’m happy they exist and I’m doing something unorthodox)

You have to instantiate the inverters as LUTs directly *AND* you have to build the latest tools yourself (I had two different binaries segfault on the design).

https://github.com/YosysHQ/nextpnr/issues/1194#issuecomment-1684724413
#verilog #fpga #ncl #asynclogic

I am building a many core #Forth processor on Lattice Semiconductor FPGAs using the open source #Yosys tools. The first products released will be two 4 core processors. 16K* 16 bit words or 10.6K * 24 bit words. Every pair of processors will communicate using 10Kbits of dual port RAM. The processors will run on the $35 #PicoIce and $30 #Upduino boards. Later there will be hundreds of cores on the larger #ULX3S #ECP5 boards.

My climate persona: @UncensoredNews
#fpga #ManyCore #introduction

Heya #fpga #embedded crowd!

Is there any #ECP5 dev board/module out there, that basically breaks out most of the IOs of the LFE5U-85?

I'm looking for something like the Colorlight i9, but for my project, i need to have the LFE5U-85.

#latticesemi #yosys #pmod

After exchanging on a #Sipeed channel about what I found with the Tang Nano 4K #FPGA examples and #HDMI output, someone, speaks me about it’s contribution of open source FPGA, with a generic FPGA HDMI driver that works on lot of FPGA (including #BlackIceMX, #icoBoard and #Icestick (both Lattice #ice40 based), #ColorLighti5 (Lattice LFE5U based), #ulx3s (Lattice #ECP5 based), #Arty7 (Xilinx #Artix7 based) and this one (Gowin #Gow1n4K based). The result is better than the official examples, and even work on my cheap (<10€) HDMI->USB acquisition device I had, where the official settings didn’t even display anything on this device. But It worked on my old computer monitor (using HDMI 2 DVI adapter).

He used DVI-PMOD that has about the same goal for a 12-pin PMOD expansion port found of lot of FPGA boards as a base for this clean and generic implementation.

Searching about what adapter supported, I found an open source FPGA project of HDMI2USB. I’m not sure my board HDMI could be used a reverse way, don’t know enough about it for now.

for everyone interested in #fpga and #opensourcehardware: radiona.org (makerspace i'm member of) recently published details about our #fpga #ECP5 development board: https://radiona.org/ulx3s/
it has been in development for some time now and already has few testers around the world but now we have "user friendly" page with details. we''re collecting interest/preorders now and first batch of boards should be available in the next few months.

Have you heard that #ECP5 FPGAs are now supported by open source toolchain? Exciting!

https://forum.mystorm.uk/t/ot-large-ecp5-fpgas-now-supported-by-open-source-tooling/488?u=biged

Which also means there's a new open source router for FPGAs which is timing driven and, as it happens, faster.

@vertigo @ddipaola

a #FOSS toolchain equivelant board with a cheap #Allwinner or #Rockchip SoC, an #ECP5 FPGA, and some RAM for each would be so excellent

I'm not exactly up to speed on #FOSS #FPGA tools, but it looks like at least one of the Lattice #ECP5 (12-84k LUTs!) chips has enough support to build an #OpenRISC SoC with DRAM support.

if the larger devices are supported, this could maybe? allow for #OSHW implementations of the #SNES , #MegaDrive , or other "16bit" era hardware

https://mobile.twitter.com/fpga_dave/status/1053290842809683968
@vertigo

Looks like there's some work being done to get a new #FPGA series supported by a #FOSS toolchain: Lattice's #ECP5 , which has up to 85k LUTs. Much nicer than the 8k limit in the #ICE40 ! https://symbiflow.github.io/prjtrellis-db/