Набрасываем на Verilator
Эта статья не является прямым продолжение статьи Время собирать пакеты , но затрагивает связанные темы. Учимся создавать артефакты в рамках концепции Инфраструктура как Артефакт. Будем разворачивать Verilator в Kubernetes.
#Verilator
Из студентов в инженеры: как перестать бояться и полюбить системную верификацию
Привет, Хабр! На связи Михаил Степанов, инженер в группе функциональной верификации YADRO. Еще в прошлом году мы с моим коллегой Романом Казаченко участвовали в хакатоне по разработке микропроцессоров как студенты, а сейчас — помогаем с задачами для SoC Design Challenge как сотрудники компании-организатора. В статье расскажем, что ждет участников трека «Системная верификация СнК» в этом году и как подготовиться к этому испытанию. Если вы не планируете участвовать в хакатоне, но вам интересно, как инженеры тестируют системы на кристалле перед запуском в производство, эта статья тоже будет вам полезна. На примере заданий хакатона я кратко объясню, что такое системная верификация, из каких блоков состоят СнК и какие инструменты используются для их тестирования.
https://habr.com/ru/companies/yadro/articles/885854/
#SoC_design #функциональная_верификация #системная_верификация #QEMU #verilog #verilator #система_на_кристалле #хакатон #SoC_Design_Challenge
Exciting update for the ROHD community! We're pleased to announce the release of ROHD Cosim v0.3.0, now supporting in/out ports and Verilator for enhanced simulation. Also, ROHD v0.6.2 is out, featuring some bug fixes and improved adder syntax in SystemVerilog. https://buff.ly/3WLth4y #rohd #opensource #hardware #hdl #cosim #verilator
🎉 Spade v0.8.0 has been released 🎉
This release extends the standard library, fixes a whole bunch of small pitfalls, and includes several improvements around tests!
The std-lib now has a higher level wrapper around #fpga block-rams, primitives for clock domain crossing, and reduce_* functions added by @0xC01DC0FFEE
Finally, improved #Verilator support allows cool stuff in tests. The video shows this being used to visualize memory accesses in my camera project
Upgraded #verilator from 5.018 to 5.020 in #MacPorts. Just waiting for the CI and merge now.
I think that it is very hard to debug complex #verilog circuits. So many things happening at the same time. So I am about to start writing C++ consistency checks for the #Verilator simulator. If this signal is this way, then that signal should be that way. Run a test, if it fails, guess at the bug, write a consistency test, and run it again.
Very different from testing each block, sadly the #J1 CPU + #Forth is one complex circuit.
#Mecrisp
IMHO #Verilator is full of shit
basically there has to be an AMS HDL (hardware definition language for analog and mixed signals, mixed with digital) for which there is a type-system, a calculus, a logic for it
not really sure what it should be, maybe a variant of π-calculus, IDK
whatever, people can only make hardware if there are tools for it; there have to be FLOSS CADs for FLOSS h/w, otherwise it just doesn't make sense, relying on a proprietary stuff just to even simulate it — #Verilator is very important in this regard, though ATM I'm not even sure it simulates correctly
and for analog there of course are Octave and Scipy/Numpy, but I can't tell how good these are for RF and transceivers; QUCS is nice too but again I can't tell how mature it is — is it only good for teaching or
not really sure what it should be, maybe a variant of π-calculus, IDK
whatever, people can only make hardware if there are tools for it; there have to be FLOSS CADs for FLOSS h/w, otherwise it just doesn't make sense, relying on a proprietary stuff just to even simulate it — #Verilator is very important in this regard, though ATM I'm not even sure it simulates correctly
and for analog there of course are Octave and Scipy/Numpy, but I can't tell how good these are for RF and transceivers; QUCS is nice too but again I can't tell how mature it is — is it only good for teaching or
I've been doing functional verification (behavioral modeling) for a while now, and it still is kinda difficult to explain, even to myself, how the synthesisable (DUT/RTL) and non-synthesisable (TB) code interact
I wouldn't be able to write my own simulator now (similar to #Verilator)
I wouldn't be able to write my own simulator now (similar to #Verilator)
If you’re using @panic ’s Nova to edit your Verilog files, you'll be happy to know that @tsalvo ‘s Verilog extension now supports linting too via verilator…
nova://extension/?id=com.tomsalvo.verilog&name=Verilog
RT from Antmicro (@antmicro)
Co-simulate CPUs from RTL in #Verilator with @renodeio to run unmodified software in a deterministic simulation. Combine precise CPU models w/ reusable #opensource I/O components to build complete systems simulating e.g. #OpenTitan SoC w/ Ibex @risc_v CPU: https://antmicro.com/blog/2023/01/cpu-rtl-co-simulation-in-renode/
Original tweet : https://twitter.com/antmicro/status/1620833104154836992
RT from fpga_kian (@splinedrive)
If you have no #fpga in your hand. just use your #riscv @mangopi_sbc to simulate your #verilog design with #verilator on it. It feels like a real fpga evalboard from form factor. Btw. it's simulate my new one cycle riscv cpu that executes raytracer code. #kianRiscV
[Video embedded in original tweet]
Original tweet : https://twitter.com/splinedrive/status/1578417325673705472
RT from Antmicro (@antmicro)
At this year's #ESSDERC - #ESSCIRC we will hold a talk on pre-silicon testing of the @GoogleOSS-sponsored @SkyWaterFoundry MPW designs using co-simulation with @renodeio and #Verilator. Visit https://www.esscirc-essderc2022.org/a-year-of-open-source-mpws to learn more. @efabless @risc_v @CHIPSAlliance
Original tweet : https://twitter.com/antmicro/status/1570769293930897413
Which packages are the 5% missing on #RISCV, what efforts are currently made and what need to be done:
https://lists.riscv.org/g/software/message/174
I would add after 1 or 2 weeks of testing that, Most JIT are missing, not only Lua (there is already a patch for RV32), PCRE, php engine, mb_strings (but they can all be used without it).
Other missing libs: libgsl25 (GNU Scientific Library), needed by Hugin, and Darktable (there is still rawtherapee). #ObsStudio is missing too.
On the sound design part, SuperCollider is missing.
On the (retrocomputer/arcade/console) emulator side missing are: openmsx, but mame, libretro (including bsnes, beetle-psx/vb/pce, desmume, etc...) are here. Missing in libretro are snes9x, and nestopia (closed source)
if Firefox (that already have patchs) and LibreOffice are not in distributions, most productivity tools already have. JHere is a partial list of what is already running on RISC-V:
* GFX: #GIMP, #Krita, #Blender, #Inkscape, #MyPaint,, #Pencil2D, #Glaxnimate, #SynfigSudio, #zopfli, #Imagemagick, #Scribus, #FontForge, #FontMatrix, #Xsane, #LaTeX, #svtAV1 (#av1)
* Audio: #LMMS, #Ardour, #MuseScore, #Fluidsynth, #VMPK, #zynaddsubfx #pipewire #sox, #Audacity, #TuxGuitar, #CheeseCutter, #SfxrQt, #BambooTracker (YM2608/OPNA), #GoatTracker (C64), #HivelyTracker (AHX, HVL), #MilkyTracker
* Photo/Video: #mpv, #pipwire, #mencoder, #ffmpeg, #shotcut, #kdenlive, #pitivi, #vlc, #mlt, #melt, #vokoscreenNG, #RecordMyDesktop, #entangle, #rawtherapee, #guvcview, #UVCcapture, #Cheese
* OS: #qemu, #uae, #DosBox
* Dev: #GCC, #LLVM, #FPGAtools, Geany, #YoSys, #QtCreator, #Fritzing, #WireShark, #GTKWave, #Verilator
* Web services: #nginx, #apache, #php, #python, #lua, #ruby
* Internet clients: #hexchat, #WeeChat, #Gajim, #Xmppc, #TelegramDesktop, #Epihany, #netsurf, #Filezilla,
* Game engines: #tic80, #LÖVE, #PyGame, #Cube2, #Scummvm, #LibRetro
* Map: #Marble, #Stellarium (stars map)
* Games (not depending on a game engine): #SuperTuxKart, #ExtremeTuxRacer, #NeverBall, #bzflag, #Wesnoth...
* SImulation: #FlightGear,
https://lists.riscv.org/g/software/message/174
I would add after 1 or 2 weeks of testing that, Most JIT are missing, not only Lua (there is already a patch for RV32), PCRE, php engine, mb_strings (but they can all be used without it).
Other missing libs: libgsl25 (GNU Scientific Library), needed by Hugin, and Darktable (there is still rawtherapee). #ObsStudio is missing too.
On the sound design part, SuperCollider is missing.
On the (retrocomputer/arcade/console) emulator side missing are: openmsx, but mame, libretro (including bsnes, beetle-psx/vb/pce, desmume, etc...) are here. Missing in libretro are snes9x, and nestopia (closed source)
if Firefox (that already have patchs) and LibreOffice are not in distributions, most productivity tools already have. JHere is a partial list of what is already running on RISC-V:
* GFX: #GIMP, #Krita, #Blender, #Inkscape, #MyPaint,, #Pencil2D, #Glaxnimate, #SynfigSudio, #zopfli, #Imagemagick, #Scribus, #FontForge, #FontMatrix, #Xsane, #LaTeX, #svtAV1 (#av1)
* Audio: #LMMS, #Ardour, #MuseScore, #Fluidsynth, #VMPK, #zynaddsubfx #pipewire #sox, #Audacity, #TuxGuitar, #CheeseCutter, #SfxrQt, #BambooTracker (YM2608/OPNA), #GoatTracker (C64), #HivelyTracker (AHX, HVL), #MilkyTracker
* Photo/Video: #mpv, #pipwire, #mencoder, #ffmpeg, #shotcut, #kdenlive, #pitivi, #vlc, #mlt, #melt, #vokoscreenNG, #RecordMyDesktop, #entangle, #rawtherapee, #guvcview, #UVCcapture, #Cheese
* OS: #qemu, #uae, #DosBox
* Dev: #GCC, #LLVM, #FPGAtools, Geany, #YoSys, #QtCreator, #Fritzing, #WireShark, #GTKWave, #Verilator
* Web services: #nginx, #apache, #php, #python, #lua, #ruby
* Internet clients: #hexchat, #WeeChat, #Gajim, #Xmppc, #TelegramDesktop, #Epihany, #netsurf, #Filezilla,
* Game engines: #tic80, #LÖVE, #PyGame, #Cube2, #Scummvm, #LibRetro
* Map: #Marble, #Stellarium (stars map)
* Games (not depending on a game engine): #SuperTuxKart, #ExtremeTuxRacer, #NeverBall, #bzflag, #Wesnoth...
* SImulation: #FlightGear,
I prefer #verilog - it is the C to #VHDL's Java, if you like. One is concise, the other verbose. One gives you plenty of rope to shoot yourself in the foot, the other tires you out. In the famous shootout, the #verilog team got the job done soonest. However, it's possible that in a complex and critical case like aerospace, the #vhdl team would make something more correct.
Many tools allow a free mix of HDLs. But the fastest simulator, #verilator is free and verilog-only.
I'm at a point where I can bind the baud rate generator, the transmit shift register, and the TileLink interface together to form the transmit-half of "the SIA core".
Question is, how would I test this? It would be grossly inconvenient to test on a cycle-by-cycle basis, since tens of thousands of clock cycles goes into a single serial bit period. Hmm....
Client Info
Server: https://mastodon.social
Version: 2025.04
Repository: https://github.com/cyevgeniy/lmst